roycpld.fit.qmsg

这是一个verilog HDL 语言的例子

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 06 14:48:45 2009 " "Info: Processing started: Fri Feb 06 14:48:45 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off RoyCPLD -c RoyCPLD " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RoyCPLD -c RoyCPLD" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "RoyCPLD EPM240T100C5 " "Info: Selected device EPM240T100C5 for design \"RoyCPLD\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM240T100I5 " "Info: Device EPM240T100I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100C5 " "Info: Device EPM570T100C5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EPM570T100I5 " "Info: Device EPM570T100I5 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" {  } {  } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0}
{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" {  } {  } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "Clk Global clock in PIN 14 " "Info: Automatically promoted signal \"Clk\" to use Global clock in PIN 14" {  } { { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 12 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "Rst Global clock " "Info: Automatically promoted signal \"Rst\" to use Global clock" {  } { { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 13 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "Rst " "Info: Pin \"Rst\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 13 -1 0 } } { "e:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "Rst" } } } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Rst } "NODE_NAME" } } { "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Rst } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0}
{ "Extra Info" "IFSAC_FSAC_START_LUT_PACKING" "" "Extra Info: Moving registers into LUTs to improve timing and density" {  } {  } 1 0 "Moving registers into LUTs to improve timing and density" 1 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_HEADER" "" "Info: Started processing fast register assignments" {  } {  } 0 0 "Started processing fast register assignments" 0 0}
{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_START" "" "Info: Starting physical synthesis optimizations" {  } {  } 0 0 "Starting physical synthesis optimizations" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "register retiming " "Info: Starting physical synthesis algorithm register retiming" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "register retiming 0 " "Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_START" "logic and register replication " "Info: Starting physical synthesis algorithm logic and register replication" {  } {  } 0 0 "Starting physical synthesis algorithm %1!s!" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_ALGO_END_SLACK" "logic and register replication 0 " "Info: Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 0 ps" {  } {  } 0 0 "Physical synthesis algorithm %1!s! complete: estimated slack improvement of %2!d! ps" 0 0}
{ "Info" "IFSYN_PHYSICAL_SYNTHESIS_END" "00:00:06 " "Info: Physical synthesis optimizations complete: elapsed time is 00:00:06" {  } {  } 0 0 "Physical synthesis optimizations complete: elapsed time is %1!s!" 0 0}