roycpld.map.qmsg

这是一个verilog HDL 语言的例子

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Feb 06 14:48:40 2009 " "Info: Processing started: Fri Feb 06 14:48:40 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off RoyCPLD -c RoyCPLD " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off RoyCPLD -c RoyCPLD" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_send_fun.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rs232_send_fun.v" { { "Info" "ISGN_ENTITY_NAME" "1 rs232_send_fun " "Info: Found entity 1: rs232_send_fun" {  } { { "rs232_send_fun.v" "" { Text "D:/CPLD Prj/RoyCPLD/rs232_send_fun.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "RoyCPLD.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file RoyCPLD.v" { { "Info" "ISGN_ENTITY_NAME" "1 RoyCPLD " "Info: Found entity 1: RoyCPLD" {  } { { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "led.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file led.v" { { "Info" "ISGN_ENTITY_NAME" "1 sm_led " "Info: Found entity 1: sm_led" {  } { { "led.v" "" { Text "D:/CPLD Prj/RoyCPLD/led.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_speed.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rs232_speed.v" { { "Info" "ISGN_ENTITY_NAME" "1 rs232_band_speed " "Info: Found entity 1: rs232_band_speed" {  } { { "rs232_speed.v" "" { Text "D:/CPLD Prj/RoyCPLD/rs232_speed.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_rec_fun.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file rs232_rec_fun.v" { { "Info" "ISGN_ENTITY_NAME" "1 rs232_rec_fun " "Info: Found entity 1: rs232_rec_fun" {  } { { "rs232_rec_fun.v" "" { Text "D:/CPLD Prj/RoyCPLD/rs232_rec_fun.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key.v" { { "Info" "ISGN_ENTITY_NAME" "1 key " "Info: Found entity 1: key" {  } { { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "RoyCPLD " "Info: Elaborating entity \"RoyCPLD\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VRFC_OBJECT_ASSIGNED_NOT_READ" "second_r RoyCPLD.v(37) " "Warning (10036): Verilog HDL or VHDL warning at RoyCPLD.v(37): object \"second_r\" assigned a value but never read" {  } { { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 37 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_band_speed rs232_band_speed:rs232_band_speed_rec " "Info: Elaborating entity \"rs232_band_speed\" for hierarchy \"rs232_band_speed:rs232_band_speed_rec\"" {  } { { "RoyCPLD.v" "rs232_band_speed_rec" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 76 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_rec_fun rs232_rec_fun:rs232_receiver " "Info: Elaborating entity \"rs232_rec_fun\" for hierarchy \"rs232_rec_fun:rs232_receiver\"" {  } { { "RoyCPLD.v" "rs232_receiver" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 85 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_send_fun rs232_send_fun:Rs232Sender " "Info: Elaborating entity \"rs232_send_fun\" for hierarchy \"rs232_send_fun:Rs232Sender\"" {  } { { "RoyCPLD.v" "Rs232Sender" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 138 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sm_led sm_led:show_sm_led " "Info: Elaborating entity \"sm_led\" for hierarchy \"sm_led:show_sm_led\"" {  } { { "RoyCPLD.v" "show_sm_led" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 147 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key key:key_check " "Info: Elaborating entity \"key\" for hierarchy \"key:key_check\"" {  } { { "RoyCPLD.v" "key_check" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 160 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "sm_led:show_sm_led\|SM_CS2_r sm_led:show_sm_led\|SM_CS1_r " "Info: Duplicate register \"sm_led:show_sm_led\|SM_CS2_r\" merged to single register \"sm_led:show_sm_led\|SM_CS1_r\", power-up level changed" {  } { { "led.v" "" { Text "D:/CPLD Prj/RoyCPLD/led.v" 65 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\", power-up level changed" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_send_fun:Rs232Sender\|tx_en rs232_send_fun:Rs232Sender\|band_start_r " "Info: Duplicate register \"rs232_send_fun:Rs232Sender\|tx_en\" merged to single register \"rs232_send_fun:Rs232Sender\|band_start_r\"" {  } { { "rs232_send_fun.v" "" { Text "D:/CPLD Prj/RoyCPLD/rs232_send_fun.v" 25 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_rec_fun:rs232_receiver\|Received_Byte_Flag_r rs232_rec_fun:rs232_receiver\|band_start_r " "Info: Duplicate register \"rs232_rec_fun:rs232_receiver\|Received_Byte_Flag_r\" merged to single register \"rs232_rec_fun:rs232_receiver\|band_start_r\"" {  } { { "rs232_rec_fun.v" "" { Text "D:/CPLD Prj/RoyCPLD/rs232_rec_fun.v" 51 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "led_d2_r data1_r\[0\] " "Info: Duplicate register \"led_d2_r\" merged to single register \"data1_r\[0\]\"" {  } { { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 62 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_STARTED_INFO" "" "Info: Performing gate-level register retiming" {  } {  } 0 0 "Performing gate-level register retiming" 0 0}
{ "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_HDR" "23 " "Info: Not allowed to move 23 registers" { { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_INPUT_DETAILS" "9 " "Info: Not allowed to move at least 9 registers because they are in a sequence of registers directly fed by input pins" {  } {  } 0 0 "Not allowed to move at least %1!d! registers because they are in a sequence of registers directly fed by input pins" 0 0} { "Info" "IOPT_MLS_RETIMING_DONT_TOUCH_REGISTERS_OUTPUT_DETAILS" "14 " "Info: Not allowed to move at least 14 registers because they feed output pins directly" {  } {  } 0 0 "Not allowed to move at least %1!d! registers because they feed output pins directly" 0 0}  } {  } 0 0 "Not allowed to move %1!d! registers" 0 0}
{ "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_HDR" "1 " "Info: Quartus II software applied gate-level register retiming to 1 clock domains" { { "Info" "IOPT_MLS_GATE_LEVEL_RETIMING_RESULTS_DETAILS" "Clk 4 2 69 " "Info: Quartus II software applied gate-level register retiming to clock \"Clk\": created 4 new registers, removed 2 registers, left 69 registers untouched" {  } {  } 0 0 "Quartus II software applied gate-level register retiming to clock \"%1!s!\": created %2!d! new registers, removed %3!d! registers, left %4!d! registers untouched" 0 0}  } {  } 0 0 "Quartus II software applied gate-level register retiming to %1!d! clock domains" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "rs232_send_fun.v" "" { Text "D:/CPLD Prj/RoyCPLD/rs232_send_fun.v" 66 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 72 -1 0 } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 62 -1 0 } } { "RoyCPLD.v" "" { Text "D:/CPLD Prj/RoyCPLD/RoyCPLD.v" 62 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } } { "key.v" "" { Text "D:/CPLD Prj/RoyCPLD/key.v" 55 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "data1_r\[2\] " "Info: Register \"data1_r\[2\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "data1_r\[3\] " "Info: Register \"data1_r\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "282 " "Info: Implemented 282 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "260 " "Info: Implemented 260 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Allocated 124 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Feb 06 14:48:43 2009 " "Info: Processing ended: Fri Feb 06 14:48:43 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}