rs232_send_fun.v

这是一个verilog HDL 语言的例子

`timescale 1ns/1ps

 module rs232_send_fun
	(
		Clk,Rst,
		band_start,band_CheckFlag,
		rs232_tx, SendByte ,
		needSend_flag
	);
	
	input Clk;
	input Rst;
	input band_CheckFlag;
	input needSend_flag;
	
	output rs232_tx ; 
	
	output band_start;	
	input wire[7:0]  SendByte;
  
	reg rs232_tx_r;
	reg band_start_r;
	reg[7:0] tx_data_temp;
	reg[3:0] num;
	reg tx_en;
	
	wire neg_chked ;
	reg neg_chk0 , neg_chk1 ;
	always @ ( posedge Clk or negedge Rst ) begin	
		if( !Rst ) begin   
			neg_chk0 <= 'b0;
			neg_chk1 <= 'b0;
		end
		else begin  
			neg_chk0 <= needSend_flag ; 
			neg_chk1 <= neg_chk0 ;
		end
	end
	
	assign neg_chked = neg_chk1 &  ~neg_chk0 ; //  下降沿  10 //高低电平分别判断一个 
			
	
	always @ ( posedge Clk or negedge Rst ) begin	
		if( !Rst ) begin 
			band_start_r <= 1'b0;
			tx_data_temp <=8'd0; 
			tx_en <= 1'b0;
		end
		else if ( neg_chked && (tx_en == 1'b0 ) ) begin
			band_start_r <= 1'b1;
			tx_data_temp <=  SendByte ; 
			tx_en <= 1'b1;
		end
		else if ( num == 4'd10) begin //数据发送完成 
			band_start_r <= 1'b0;
			tx_en <= 1'b0;
		end
	end
	
	
	always @ ( posedge Clk or negedge Rst ) begin	
		if( !Rst ) begin
			rs232_tx_r <= 1'b1; 
			num <= 4'h0; 
		end
		else if( tx_en) begin
			if( band_CheckFlag ) begin
				case (num)  
					4'd0: rs232_tx_r <= 1'b0; 	//发送起始位
					4'd1: rs232_tx_r <= tx_data_temp[0] ;
					4'd2: rs232_tx_r <= tx_data_temp[1] ;
					4'd3: rs232_tx_r <= tx_data_temp[2] ;
					4'd4: rs232_tx_r <= tx_data_temp[3] ;
					4'd5: rs232_tx_r <= tx_data_temp[4] ;
					4'd6: rs232_tx_r <= tx_data_temp[5] ;
					4'd7: rs232_tx_r <= tx_data_temp[6] ;
					4'd8: rs232_tx_r <= tx_data_temp[7] ;
					4'd9: rs232_tx_r <= 1'b1;	//发送结束位
					default :;
				endcase
				num <= num + 4'd1;
			end			
			else if( num == 4'd10) 
				num <= 4'd0;
		end
	end
	
	assign band_start = band_start_r ;
	assign rs232_tx = rs232_tx_r ; 

endmodule