led.v

这是一个verilog HDL 语言的例子

`timescale 1ns/1ps 

module sm_led
	(
		Clk,Rst,
		SM_CS1,SM_CS2, SM_db,
		data1,data2
	);
input Clk; 
input Rst;

output SM_CS1;
output SM_CS2;
output[6:0] SM_db;  //7段数码管（不包括小数点）
	// Module contents
input [3:0] data1;  
input[3:0] data2;  

reg [24:0] cnt;

initial begin
	cnt = 25'd0;
end

//-------------------------------------------------------------------------------
/*	共阴极 :不带小数点
              ;0,  1,  2,  3,  4, 5,  6,  7,  
      db      3fh,06h,5bh,4fh,66h,6dh,7dh,07h 
              ;8,  9, a,  b,   c,  d,  e,  f , 灭   
      db      7fh,6fh,77h,7ch,39h,5eh,79h,71h,00h*/
parameter	seg0	= 7'h3f,
			seg1	= 7'h06,
			seg2	= 7'h5b,
			seg3	= 7'h4f,
			seg4	= 7'h66,
			seg5	= 7'h6d,
			seg6	= 7'h7d,
			seg7	= 7'h07,
			seg8	= 7'h7f,
			seg9	= 7'h6f,
			sega	= 7'h77,
			segb	= 7'h7c,
			segc	= 7'h39,
			segd	= 7'h5e,
			sege	= 7'h79,
			segf	= 7'h71;

parameter	cnt_limit = 2000;//24'hffffff ;//4000;
parameter	cnt_limit_by2 = cnt_limit/2;//2000;

always @ ( posedge Clk or negedge Rst ) begin
	if( !Rst)
		cnt<=25'd0;
	else begin
		if( cnt < cnt_limit )
			cnt <= cnt + 20'd1;
		else
			cnt <= 25'd0;
	end
end			

wire [3:0] num;
reg SM_CS1_r,SM_CS2_r;

always @ ( posedge Clk   ) begin 
	if(  cnt<cnt_limit_by2 ) begin
		SM_CS1_r<=1'b1;
		SM_CS2_r<=1'b0;
		//num<=  data1;
	end
	else begin
		SM_CS1_r<=1'b0;
		SM_CS2_r<=1'b1;
		//num<=  data2;		
	end 
end

assign num = SM_CS1_r?data1:data2;

reg [6:0] SM_db_r;
always @ ( posedge Clk or negedge Rst ) begin
	if( !Rst) begin
		SM_db_r<=7'h00;   // 灭
	end
	else begin
		case (num) 
			4'h0: SM_db_r <= seg0;
			4'h1: SM_db_r <= seg1;
			4'h2: SM_db_r <= seg2;
			4'h3: SM_db_r <= seg3;
			4'h4: SM_db_r <= seg4;
			4'h5: SM_db_r <= seg5;
			4'h6: SM_db_r <= seg6;
			4'h7: SM_db_r <= seg7;
			4'h8: SM_db_r <= seg8;
			4'h9: SM_db_r <= seg9;
			4'ha: SM_db_r <= sega;
			4'hb: SM_db_r <= segb;
			4'hc: SM_db_r <= segc;
			4'hd: SM_db_r <= segd;
			4'he: SM_db_r <= sege;
			4'hf: SM_db_r <= segf;
			default : 
				SM_db_r<=7'h00;   // 灭
		endcase
	end
end

assign SM_CS1=SM_CS1_r;
assign SM_CS2=SM_CS2_r;

assign SM_db=SM_db_r;

endmodule