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📄 roycpld.v

📁 这是一个verilog HDL 语言的例子
💻 V
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`timescale 1ns/1ps

module RoyCPLD
	(
		Clk,Rst,
		SM_CS1,SM_CS2, SM_db,
		rs232_rx,rs232_tx,
		led_d0,led_d1,led_d2,led_d3,
		bell,
		sw0,sw1,sw2,sw3
	);
input Clk;
input Rst;
input rs232_rx;
input sw0,sw1,sw2,sw3;
output rs232_tx;

output SM_CS1;
output SM_CS2;
output[6:0] SM_db;  //7段数码管(不包括小数点)
output led_d0,led_d1;
output led_d2,led_d3;
output bell;

wire[3:0] data1;
wire[3:0] data2;

reg[3:0] data1_r;
//reg[3:0] data2_r;
reg[27:0] led_cnt_r;

//reg led_d0_r,led_d1_r;
reg led_d2_r,led_d3_r;
reg bell_r;
 
wire rs232_needSend_flag;
reg second_r;
 

always @ ( posedge Clk or negedge Rst) begin
	if(!Rst)  begin
		led_cnt_r<=28'd0; 
		data1_r<=4'h0;
		//data2_r<=4'h0;//4'h6;
		second_r <= 1'b0;
		led_d2_r <=1'b0;
		led_d3_r <=1'b1;
		
	end
	else  begin
		if( led_cnt_r > 28'h2FAF080 ) begin
			led_cnt_r<=0;
			data1_r<=data1_r+4'h1;
			second_r <= 1'b1;
			led_d2_r <= ~led_d2_r ;
			led_d3_r <= ~led_d3_r ;
		end
		else begin
			led_cnt_r<=led_cnt_r+24'h1;  	
			second_r <= 1'b0; 
		end
	end
end 

//assign rs232_needSend_flag = second_r ;


wire band_start_rec;
wire band_CheckFlag_rec;
wire[7:0] rs232_rec_byte;

rs232_band_speed rs232_band_speed_rec
	(
		.band_Clk(Clk), .band_Rst(Rst),
		.band_start(band_start_rec), .band_CheckFlag(band_CheckFlag_rec) 
	);
	
rs232_rec_fun rs232_receiver
	(
		.Clk(Clk), .Rst(Rst),
		.band_start(band_start_rec), .band_CheckFlag(band_CheckFlag_rec),
		.rs232_rx_in(rs232_rx) , .RecByte_out(rs232_rec_byte),
		.Received_Byte_Flag( rs232_needSend_flag )  
		/* .Received_Byte_Flag(  ) */
	);

always @ ( posedge Clk or negedge Rst ) begin
	if( !Rst ) begin		
		//led_d0_r <=1'b0;
		//led_d1_r <=1'b0;
		//led_d2_r <=1'b0;
		//led_d3_r <=1'b0;
		bell_r <=1'b0;
	end
	else begin
		if( band_CheckFlag_rec ) begin
			//led_d0_r <= 1'b1;
			//led_d1_r <= 1'b1;
			//led_d2_r <= 1'b1;
			//led_d3_r <= 1'b1;
			bell_r <=1'b1;
		end
		else begin
			//led_d0_r <= 1'b0;
			//led_d1_r <= 1'b0;
			//led_d2_r <= 1'b0;
			//led_d3_r <= 1'b0;
			bell_r <=1'b0;
		end
	end
end


assign data1= data1_r;// rs232_rec_byte[7:4] ; //data1_r;
assign data2=  rs232_rec_byte[3:0] ;//data2_r;

 
wire band_start_send;
wire band_CheckFlag_send;
wire[7:0] rs232_send_byte;

assign rs232_send_byte =  rs232_rec_byte;//{ 4'h0 , data1_r };// rs232_rec_byte;



rs232_band_speed Rs232_band_speed_Send
	(
		.band_Clk(Clk), .band_Rst(Rst),
		.band_start(band_start_send), .band_CheckFlag(band_CheckFlag_send) 
	);

rs232_send_fun Rs232Sender
	(
		.Clk(Clk),.Rst(Rst),
		.band_start(band_start_send),.band_CheckFlag(band_CheckFlag_send),
		.rs232_tx(rs232_tx), .SendByte(rs232_send_byte),
		.needSend_flag(rs232_needSend_flag)
	);
 
 
 
sm_led show_sm_led
	(
		.Clk(Clk),.Rst(Rst),
		.SM_CS1(SM_CS1),.SM_CS2(SM_CS2), .SM_db(SM_db),
		.data1(data1),.data2(data2)
	);

//assign  led_d0 = led_d0_r;
//assign  led_d1 = led_d1_r;
assign  led_d2 = led_d2_r;
assign  led_d3 = led_d3_r;
assign  bell = bell_r;

key key_check
	(
		.Clk(Clk),.Rst(Rst),
		.sw0(sw0),.sw1(sw1),.sw2(sw2),.sw3(sw3),
		.led_d0(led_d0),.led_d1(led_d1)
	);

endmodule

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