key.v

来自「这是一个verilog HDL 语言的例子」· Verilog 代码 · 共 79 行

`timescale 1ns/1ps

module key
	(
		Clk,Rst,
		sw0,sw1,sw2,sw3,
		led_d0,led_d1
	);
	
input Clk,Rst;
input sw0,sw1,sw2,sw3;
output led_d0,led_d1;

wire[3:0] key_neg;
reg[3:0] key_neg_now;
reg[3:0] key_neg_pre;

always @ (posedge Clk or negedge Rst) begin
	if( !Rst) begin
		key_neg_now <= 4'h0;
		key_neg_pre <= 4'h0;
	end
	else begin
		key_neg_now <= { sw3,sw2,sw1,sw0 };
		key_neg_pre <= key_neg_now;
	end
end

assign key_neg = key_neg_pre & (~key_neg_now); //检查是下降沿

reg [19:0] cnt;
always @ ( posedge Clk or negedge Rst) begin
	if( !Rst)
		cnt <= 20'd0;
	else if (key_neg)
		cnt <= 20'd0;
	else
		cnt <= cnt + 1'b1;
end

//检查20ms后是否还是按下状态，即是否还是低电平
wire[3:0] key_state;
reg[3:0] key_state_now;
reg[3:0] key_state_pre;

always @ (posedge Clk or negedge Rst) begin
	if( !Rst) begin
		key_state_now <= 4'hF;
		key_state_pre <= 4'hF;
	end
	else begin
		if ( cnt ==  20'hfffff )
			key_state_now <= { sw3,sw2,sw1,sw0 };
		key_state_pre <= key_state_now;
	end
end

assign key_state = key_state_pre & (~key_state_now); // 

reg led_d0_r,led_d1_r;

always @ ( posedge Clk or negedge Rst ) begin
	if( !Rst ) begin
		led_d0_r <= 'b1;
		led_d1_r <= 'b0;
	end
	else begin
		if( key_state ) begin
			led_d0_r <= ~led_d0_r;
			led_d1_r <= ~led_d1_r;		
		end
	end
end

assign  led_d0 = led_d0_r;
assign  led_d1 = led_d1_r;


endmodule