roycpld.fit.smsg

这是一个verilog HDL 语言的例子

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Feb 06 14:48:45 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off RoyCPLD -c RoyCPLD
Info: Selected device EPM240T100C5 for design "RoyCPLD"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "Clk" to use Global clock in PIN 14
Info: Automatically promoted signal "Rst" to use Global clock
Info: Pin "Rst" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Starting physical synthesis optimizations
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm logic and register replication
Info: Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 0 ps
Info: Physical synthesis optimizations complete: elapsed time is 00:00:06
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter can't place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter can't place all nodes on current device -- Fitter will automatically make another fitting attempt and tightly pack logic elements
Info: Starting register packing
Info: Fitter is using Minimize Area packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:01
Info: Fitter placement operations beginning
Info: Starting physical synthesis optimizations
Info: Starting physical synthesis algorithm register retiming
Info: Physical synthesis algorithm register retiming complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm logic and register replication
Info: Physical synthesis algorithm logic and register replication complete: estimated slack improvement of 0 ps
Info: Starting physical synthesis algorithm register unpacking
Info: Physical synthesis algorithm register unpacking complete: estimated slack improvement of 0 ps
Info: Physical synthesis optimizations complete: elapsed time is 00:00:03
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:05
Info: Estimated most critical path is register to register delay of 10.082 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y3; Fanout = 3; REG Node = 'led_cnt_r[3]'
    Info: 2: + IC(1.557 ns) + CELL(0.200 ns) = 1.757 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~666'
    Info: 3: + IC(0.980 ns) + CELL(0.200 ns) = 2.937 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~667'
    Info: 4: + IC(0.980 ns) + CELL(0.200 ns) = 4.117 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~668'
    Info: 5: + IC(0.980 ns) + CELL(0.200 ns) = 5.297 ns; Loc. = LAB_X3_Y3; Fanout = 1; COMB Node = 'LessThan0~669'
    Info: 6: + IC(0.266 ns) + CELL(0.914 ns) = 6.477 ns; Loc. = LAB_X3_Y3; Fanout = 32; COMB Node = 'LessThan0~671'
    Info: 7: + IC(1.845 ns) + CELL(1.760 ns) = 10.082 ns; Loc. = LAB_X6_Y3; Fanout = 4; REG Node = 'led_cnt_r[22]'
    Info: Total cell delay = 3.474 ns ( 34.46 % )
    Info: Total interconnect delay = 6.608 ns ( 65.54 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 13% of the available device resources. Peak interconnect usage is 13%
    Info: The peak interconnect region extends from location X0_Y0 to location X8_Y5
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Allocated 156 megabytes of memory during processing
    Info: Processing ended: Fri Feb 06 14:49:00 2009
    Info: Elapsed time: 00:00:15