rs232_speed.v

这是一个verilog HDL 语言的例子

`timescale 1ns/1ps

module rs232_band_speed
	( 
	band_Clk,band_Rst,
	band_start,band_CheckFlag 
	);
	
input band_Clk;
input band_Rst;
input band_start;
output band_CheckFlag; 

/*
 50Mhz / bps 

parameter 		bps9600 	= 5207,	//波特率为9600bps
			 	bps19200 	= 2603,	//波特率为19200bps
				bps38400 	= 1301,	//波特率为38400bps
				bps57600 	= 867,	//波特率为57600bps
				bps115200	= 433;	//波特率为115200bps

parameter 		bps9600_2 	= 2603,
				bps19200_2	= 1301,
				bps38400_2	= 650,
				bps57600_2	= 433,
				bps115200_2 = 216;  
*/

reg[15:0] band_cnt;

	//以下波特率分频计数值可参照上面的参数进行更改
`define		BPS_PARA		5207	//波特率为9600时的分频计数值
`define 	BPS_PARA_2		2603	//波特率为9600时的分频计数值的一半，用于数据采样


always @ ( posedge band_Clk or negedge band_Rst) begin
	if(!band_Rst)
		band_cnt<= 16'h00;
	else if( !band_start ||  band_cnt == `BPS_PARA )  begin // ***** 千万注意这里：　!band_start  
		band_cnt <=16'h00; 
	end
	else 
		band_cnt <= band_cnt + 16'h01;
end

reg band_CheckFlag_r;
//reg bell_r;

always @ ( posedge band_Clk or negedge band_Rst) begin
	if(!band_Rst) begin
		band_CheckFlag_r<= 1'b0;
		//bell_r <= 1'b0;
	end
	else  if( band_cnt == `BPS_PARA_2 )  begin
		band_CheckFlag_r<= 1'b1;
		//bell_r <= 1'b1;
	end 
	else begin
		band_CheckFlag_r<= 1'b0; 
		//bell_r <= 1'b0;
	end
end

assign band_CheckFlag=band_CheckFlag_r;
//assign bell = bell_r;

endmodule