roycpld.tan.rpt

这是一个verilog HDL 语言的例子

; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM240T100C5       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 100 MHz            ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clk             ;                    ; User Pin ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clk'                                                                                                                                                                                                                                                                                                  ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------+----------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                               ; To                                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+----------------------------------------------------+----------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[27]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[26]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[24]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[25]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[23]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[19]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[20]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[21]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.172 ns                               ; 98.31 MHz ( period = 10.172 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[22]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.463 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[9]                                       ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[10]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[11]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[12]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[14]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[15]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;
; -0.162 ns                               ; 98.41 MHz ( period = 10.162 ns )                    ; led_cnt_r[25]                                      ; led_cnt_r[13]                                      ; Clk        ; Clk      ; 10.000 ns                   ; 9.291 ns                  ; 9.453 ns                ;