dec.v

verilog开发的PCI target模块

`timescale 1ns / 1ps
/*************************************************************
* Project Name: l2f_recoder
* File Name: DEC.v
*
* Description: This is the decoder module, and it's used to
*		decode the AD and C/BE# on the primary bus, also it
*		provides signals for other modules 
*
* modification history: 
*        1.0, 2008-03-07, qipeihong([e-mail]) Written
*
* Copyright: 2009-2014 ICT,CAS.
* 
**************************************************************/
// ----------------------------------------------------------
// history:
// ----------------------------------------------------------

module DEC(
    PCI_CLK,
    PCI_RESETn,
    PCI_FRAMEn,
    PCI_IRDYn,
    PCI_IDSEL,
    ST_FRAME,
    PCI_AD_in,
    PCI_CBEn_in,
    TYPE0R,
    TYPE0W,
    BA0_HIT,
    BA1_HIT,
    BK_ADDR,
    MEMR,
    MEMW,
    IO_EN,
    MEM_EN,
    BUS_MASTER_EN,
    BASE_ADDR0,
    BASE_ADDR1
);

    // ------------------------------------------------------
    //                  PCI Interface
    // ------------------------------------------------------
        input               PCI_CLK;        // system clock signal
        input               PCI_RESETn;     // system reset signal
        input               PCI_FRAMEn;	    // primary bus FRAME# signal
        input   [31:0]      PCI_AD_in;      // primary bus AD input signal
        input   [3:0]       PCI_CBEn_in;    // primary bus C/BE# input signal
        input               PCI_IRDYn;      // primary bus IRDY# signal
        input               PCI_IDSEL;      // primary bus PCI_IDSEL signal

    // ------------------------------------------------------
    // config space registers, it provides the bus number of 
    // primary bus, secondary bus and subordinate bus, and
    // the base and limit registers of I/O and memory space	
    // ------------------------------------------------------
        input   [31:20]     BASE_ADDR0;
        input   [31:20]     BASE_ADDR1;
        input               IO_EN;
        input               MEM_EN;
        input               BUS_MASTER_EN;

        output   [19:0]     BK_ADDR;        // back end address
        output              ST_FRAME;       // start FRAME# is the negedge of FRAME#
        output              TYPE0R;         // type0 read
        output              TYPE0W;         // type0 write
        output              MEMR;           // memory read
        output              MEMW;           // memory write
        output              BA0_HIT;
        output              BA1_HIT;


// ------------------------------
// Delay FRAME# 1 clock cycle
// ------------------------------		
reg PCI_FRAMEn_D;
always @ (posedge PCI_CLK, negedge PCI_RESETn) begin
    if(!PCI_RESETn)
        PCI_FRAMEn_D <= 1'b1;
    else
        PCI_FRAMEn_D <= #5 PCI_FRAMEn;
end

// ---------------------------------------------------
// ST_FRAME is the negedge of FRAME# on primary bus
// ---------------------------------------------------
wire ST_FRAME;	
assign ST_FRAME = !PCI_FRAMEn & PCI_FRAMEn_D;

// ==========================================================
// decode the command ---- treat the Memory read multiple 
// and memory read line as the memory read, treat the 
// memory write and invalidate as the memory write
// ==========================================================
assign TYPE0R = ST_FRAME & (PCI_CBEn_in == 4'b1010) & PCI_IDSEL & PCI_AD_in[1:0] == 2'b00 & PCI_AD_in[10:8] == 3'b000;
assign TYPE0W = ST_FRAME & (PCI_CBEn_in == 4'b1011) & PCI_IDSEL & PCI_AD_in[1:0] == 2'b00 & PCI_AD_in[10:8] == 3'b000;

assign MEMR = ST_FRAME & ( PCI_CBEn_in == 4'b0110 | PCI_CBEn_in == 4'b1100 | PCI_CBEn_in == 4'b1110 ) & (MEM_EN == 1);
assign MEMW = ST_FRAME & ( PCI_CBEn_in == 4'b0111 | PCI_CBEn_in == 4'b1111) & (MEM_EN == 1);

assign BA0_HIT = ST_FRAME & (PCI_AD_in[31:20] == BASE_ADDR0);
assign BA1_HIT = ST_FRAME & (PCI_AD_in[31:20] == BASE_ADDR1);

// ==================================================
// decode AD bus and C/BE# bus
// ==================================================
reg [31:0] PCI_ADDR;
reg [3:0] PCI_COMMAND;
always @ (posedge PCI_CLK, negedge PCI_RESETn) begin
    if(!PCI_RESETn) begin
        PCI_ADDR <= 32'b0;
        PCI_COMMAND <= 4'b0;
    end
    else if(ST_FRAME) begin
        PCI_ADDR <= PCI_AD_in;
        PCI_COMMAND <= PCI_CBEn_in;
    end
    else begin
        PCI_ADDR <= PCI_ADDR;
        PCI_COMMAND <= PCI_COMMAND;
    end
end

// -----------------------
// back end address
// -----------------------
assign BK_ADDR = PCI_ADDR[19:0];

endmodule