mem_target.v

verilog开发的PCI target模块

`timescale 1ns / 1ps
/*************************************************************
* Project Name: PCI-PCI Bridge IP core
* File Name: MEM_Target.v
*
* Description: This MEM_Target is used to generate the
*		DEVSEL#, TRDY# and STOP# when the primary interface
*		is a memory read/write transaction
*
* Company : ICT@Spatial Information Technology Lab
* Author: qipeihong([e-mail])
* Tool versions:  Xilinx ISE 9.2i + ModelSim SE 6.2b
* Create Date: 2008-03-24
* Revision 0.01 - File Created
*
* Additional Comments:
* 
**************************************************************/
// ----------------------------------------------------------
// history:
// ----------------------------------------------------------

module MEM_Target(
    PCI_CLK,
    PCI_RESETn,
    PCI_FRAMEn,
    PCI_IRDYn,
    PCI_AD_in,
    BK_DATA_in,
    MEMR,
    MEMW,
    MEM_DEVSELn,
    MEM_TRDYn,
    MEM_STOPn,
    MEM_DTS_OE,
    MEM_AD_OE,
    MEMR_Data_out,
//  MEM_ADDR_out,
    BK_DATA_out,
    BK_EN,
    BK_RWn,    // 1 write, 0 read
    BK_CS0,
    BK_CS1,
    BA0_HIT,
    BA1_HIT
);

// --------------------------------------------------
//              input signals
// --------------------------------------------------
    input               PCI_CLK;
    input               PCI_RESETn;
    input               PCI_FRAMEn;
    input               PCI_IRDYn;
    input   [31:0]      PCI_AD_in;
    input               MEMR;
    input               MEMW;
    input               BA0_HIT;
    input               BA1_HIT;
    input   [31:0]      BK_DATA_in;

// --------------------------------------------------
//              output signals
// --------------------------------------------------
    output              MEM_DEVSELn;
    output              MEM_TRDYn;
    output              MEM_STOPn;
    output              MEM_DTS_OE;
    output              MEM_AD_OE;
    output  [31:0]      MEMR_Data_out;
//  output  [19:0]      MEM_ADDR_out;
    output  [31:0]      BK_DATA_out;
    output              BK_EN;
    output              BK_RWn;
    output              BK_CS0;
    output              BK_CS1;

    reg     MEM_DEVSELn;
    reg     MEM_TRDYn;
    reg     MEM_STOPn;
    reg     MEM_DTS_OE;
    reg     MEM_AD_OE;
    reg     MEMR_Data_out;
    reg     BK_DATA_out;
    reg     BK_EN;
    reg     BK_RWn;
    reg     BK_CS0;
    reg     BK_CS1;

/************************************************
*           declaration of state machine        *
*************************************************/
parameter
    IDLE = 0, 
    WAIT = 1,
    TURN_AR = 2,
    MEM_READ = 3,
    MEM_WRITE = 4,
    BACKOFF = 5,
    DISCON = 6;

reg	[2:0]   CState;	    // current state
reg	[2:0]   NState;     // next state
/************************************************
*                end declaration                *
*************************************************/

always @ (posedge PCI_CLK, negedge PCI_RESETn) begin
    if(!PCI_RESETn)
        CState <= #1 IDLE;
    else
        CState <= #1 NState;
end

always @ * begin
    case(CState)	// synopsys parallel_case full_case
        IDLE: begin
            if((MEMW || MEMR) && (BA0_HIT || BA1_HIT))
                NState = WAIT;
            else
                NState = IDLE;
        end

        WAIT: begin
            if(!BK_RWn) begin   // mem_read
               NState = TURN_AR;
            end
            else begin   // memory write
               NState = MEM_WRITE;
            end
        end

        TURN_AR: begin
            NState = MEM_READ;
        end

        MEM_READ: begin
            if(!PCI_FRAMEn && !PCI_IRDYn)
                NState = DISCON;
            else
                NState = BACKOFF;
        end

        MEM_WRITE: begin
            if(!PCI_FRAMEn && !PCI_IRDYn)
                NState = DISCON;
            else
                NState = BACKOFF;
        end

        BACKOFF: begin  // prepare to release pci bus
            NState = IDLE;
        end

        DISCON: begin
            if(PCI_FRAMEn)
                NState = IDLE;
            else
                NState = DISCON;
        end
        
        default:
            NState = IDLE;
    endcase
end

reg stop_flag;

always @ (posedge PCI_CLK, negedge PCI_RESETn) begin
    if(!PCI_RESETn) begin
        MEM_DEVSELn <= 1'b1;
        MEM_TRDYn <= 1'b1;
        MEM_STOPn <= 1'b1;
        MEM_DTS_OE <= 1'b0;
        MEM_AD_OE <= 1'b0;
        MEMR_Data_out <= 32'b0;
        BK_DATA_out <= 32'b0;
        BK_EN <= 1'b0;
        BK_RWn <= 1'b0;     // default is read
        BK_CS0 <= 1'b0;
        BK_CS1 <= 1'b0;
    end
    else begin
        case(CState)    // synopsys parallel_case full_case
            IDLE: begin
                MEM_DEVSELn <= 1'b1;
                MEM_TRDYn <= 1'b1;
                MEM_STOPn <= 1'b1;
                MEM_DTS_OE <= 1'b0;
                MEM_AD_OE <= 1'b0;
                if(MEMW) begin
                    BK_RWn <= 1'b1;
                    if(BA0_HIT) begin
                        BK_CS0 <= 1'b1;
                        BK_CS1 <= 1'b0;
                    end
                    else if(BA1_HIT) begin
                        BK_CS0 <= 1'b0;
                        BK_CS1 <= 1'b1;
                    end
                    else begin
                        BK_CS0 <= 1'b0;
                        BK_CS1 <= 1'b0;
                    end
                end
                else if(MEMR) begin
                    BK_RWn <= 1'b0;
                    if(BA0_HIT) begin
                        BK_CS0 <= 1'b1;
                        BK_CS1 <= 1'b0;
                    end
                    else if(BA1_HIT) begin
                        BK_CS0 <= 1'b0;
                        BK_CS1 <= 1'b1;
                    end
                    else begin
                        BK_CS0 <= 1'b0;
                        BK_CS1 <= 1'b0;
                    end
                end
                else begin
                    BK_RWn <= 1'b0;
                    BK_CS0 <= 1'b0;
                    BK_CS1 <= 1'b0;
                end
            end

            WAIT: begin // PCI target is a medium device, so insert a wait cycle
                MEM_DEVSELn <= #1 1'b1;
                MEM_TRDYn <= 1'b1;
                MEM_STOPn <= 1'b1;
                MEM_DTS_OE <= 1'b1;
            end

            TURN_AR: begin
                MEM_DEVSELn <= 1'b0;
                MEM_DTS_OE <= 1'b1;
                MEM_AD_OE <= 1'b1;
                BK_EN <= 1'b1;
                if(!PCI_FRAMEn && !PCI_IRDYn) begin     // PCI target can't support burst read transaction
                    stop_flag <= 1'b1;
                end
                else begin
                    stop_flag <= 1'b0;
                end
            end

            MEM_READ: begin
                MEM_DEVSELn <= 1'b0;
                MEM_TRDYn <= 1'b0;
                MEM_DTS_OE <= 1'b1;
                MEM_AD_OE <= 1'b1;
                MEMR_Data_out <= BK_DATA_in;
                BK_EN <= 1'b0;
                if(stop_flag)
                    MEM_STOPn <= 1'b0;
                else
                    MEM_STOPn <= 1'b1;
            end

            MEM_WRITE: begin
                MEM_DEVSELn <= 1'b0;
                MEM_TRDYn <= 1'b0;
                MEM_DTS_OE <= 1'b1;
                MEM_AD_OE <= 1'b0;
                BK_DATA_out <= PCI_AD_in;
                BK_EN <= 1'b1;
                if(!PCI_FRAMEn && !PCI_IRDYn)
                    MEM_STOPn <= 1'b0;
                else
                    MEM_STOPn <= 1'b1;
            end

            BACKOFF: begin
                MEM_DEVSELn <= 1'b1;
                MEM_TRDYn <= 1'b1;
                MEM_STOPn <= 1'b1;
                MEM_DTS_OE <= 1'b1;
                MEM_AD_OE <= 1'b0;
                BK_EN <= 1'b0;
                BK_RWn <= 1'b0;
                BK_CS0 <= 1'b0;
                BK_CS1 <= 1'b0;
                stop_flag <= 1'b0;
            end

            DISCON: begin
                if(PCI_FRAMEn) begin
                    MEM_DEVSELn <= 1'b1;
                    MEM_TRDYn <= 1'b1;
                    MEM_STOPn <= 1'b1;
                    MEM_DTS_OE <= 1'b1;
                    MEM_AD_OE <= 1'b0;
                    BK_EN <= 1'b0;
                    BK_RWn <= 1'b0;
                    BK_CS0 <= 1'b0;
                    BK_CS1 <= 1'b0;
                    stop_flag <= 1'b0;
                end
                else begin
                    MEM_DEVSELn <= 1'b0;
                    MEM_TRDYn <= 1'b1;
                    MEM_STOPn <= 1'b0;
                    MEM_DTS_OE <= 1'b1;
                    if(!BK_RWn)
                        MEM_AD_OE <= 1'b1;
                    else
                        MEM_AD_OE <= 1'b0;
                end
            end

            default: begin
                MEM_DEVSELn <= 1'b1;
                MEM_TRDYn <= 1'b1;
                MEM_STOPn <= 1'b1;
                MEM_DTS_OE <= 1'b0;
                MEM_AD_OE <= 1'b0;
                BK_EN <= 1'b0;
                BK_RWn <= 1'b0;
                BK_CS0 <= 1'b0;
                BK_CS1 <= 1'b0;
                stop_flag <= 1'b0;
            end
	
        endcase
    end
end

endmodule