pci_target.v

来自「verilog开发的PCI target模块」· Verilog 代码 · 共 246 行

`timescale 1ns / 1ps
/*************************************************************
* Project Name: L2F_Recoder
* File Name: PCI_TARGET.v
*
* Description: This is the top module, it contains no logic
*      besides module instantiation and connection, also,
*      inout ports should be changed to input and output
*      ports for internal module to use
*
* Company : ICT@Spatial Information Technology Lab
* Author: qipeihong([e-mail])
* Tool versions:  Xilinx ISE 9.2i
* Create Date: 2008-03-15
* Revision 0.01 - File Created
*
* Additional Comments:
* 
**************************************************************/
// ----------------------------------------------------------
// history:
// ----------------------------------------------------------

module PCI_TARGET(
    PCI_CLK,
    PCI_RESETn,
    PCI_AD,
    PCI_CBEn,
    PCI_PAR,
    PCI_FRAMEn,
    PCI_IRDYn,
    PCI_IDSEL,
    PCI_DEVSELn,
    PCI_TRDYn,
    PCI_STOPn,
    PCI_PERRn,
    PCI_SERRn,
    PCI_INTAn,
    BK_ADDR,
    BK_DATA_in,
    BK_DATA_out,
    BK_CS0,
    BK_CS1,
    BK_CLK,
    BK_RESETn,
    BK_RWn,
    BK_EN,
    DEV0_INTn,
    DEV1_INTn
);

// --------------------------------------------------
// >>>>>>>>>>>>>>>>>> PCI Interface <<<<<<<<<<<<<<<<<
// --------------------------------------------------
    input             PCI_CLK;
    input             PCI_RESETn;
    inout   [31:0]    PCI_AD;
    input   [3:0]     PCI_CBEn;
    inout             PCI_PAR;
    input             PCI_FRAMEn;
    input             PCI_IRDYn;
    input             PCI_IDSEL;
    output            PCI_DEVSELn;
    output            PCI_TRDYn;
    output            PCI_STOPn;
    inout             PCI_PERRn;
    output            PCI_INTAn;
    output            PCI_SERRn;
// -------------------------------------------------------
// >>>>>>>>>>>>>>>>>> back end Interface <<<<<<<<<<<<<<<<<
// ------------------------------------------------------- 
    input               DEV0_INTn;
    input               DEV1_INTn;    
    input   [31:0]      BK_DATA_in;
    output  [19:0]      BK_ADDR;
    output  [31:0]      BK_DATA_out;
    output              BK_CS0;
    output              BK_CS1;
    output              BK_CLK;
    output              BK_RESETn;
    output              BK_RWn;
    output              BK_EN;
    
// ------------------------------------------
// back end clock and reset signals
// ------------------------------------------
    assign BK_CLK = PCI_CLK;
    assign BK_RESETn = PCI_RESETn;
    
// ------------------------------------------
// pci interrupt signal
// ------------------------------------------
    assign PCI_INTAn = DEV0_INTn && DEV1_INTn;
    
    wire         PAR_in;
    wire         ST_FRAME;
    wire         TYPE0R;
    wire         TYPE0W;
    wire         BA0_HIT;
    wire         BA1_HIT;
    wire         MEMR;
    wire         MEMW;
    wire         IO_EN;
    wire         MEM_EN;
    wire         BUS_MASTER_EN;
    wire [31:20] BASE_ADDR0;
    wire [31:20] BASE_ADDR1;
    
    wire [31:0]  PCI_AD_in;

    DEC decoder(
        .PCI_CLK        (PCI_CLK),
        .PCI_RESETn     (PCI_RESETn),
        .PCI_FRAMEn     (PCI_FRAMEn),
        .PCI_IRDYn      (PCI_IRDYn),
        .PCI_IDSEL      (PCI_IDSEL),
        .ST_FRAME       (ST_FRAME),
        .PCI_AD_in      (PCI_AD_in),
        .PCI_CBEn_in    (PCI_CBEn),
        .TYPE0R         (TYPE0R),
        .TYPE0W         (TYPE0W),
        .BA0_HIT        (BA0_HIT),
        .BA1_HIT        (BA1_HIT),
        .BK_ADDR        (BK_ADDR),
        .MEMR           (MEMR),
        .MEMW           (MEMW),
        .IO_EN          (IO_EN),
        .MEM_EN         (MEM_EN),
        .BUS_MASTER_EN  (BUS_MASTER_EN),
        .BASE_ADDR0     (BASE_ADDR0),
        .BASE_ADDR1     (BASE_ADDR1)
    );
    
    wire        CFG_TRDYn;
    wire [31:0] CFG_DATA_out;
    wire        CONFIG_READ;
    wire        CONFIG_WRITE;
    wire        CFG_AD_OE;
    wire        CFG_DTS_OE;
    wire        CFG_DEVSELn;
    
    config_space CFG_SPACE(
        .PCI_CLK        (PCI_CLK),
        .PCI_RESETn     (PCI_RESETn),
        .PCI_AD         (PCI_AD_in),
        .PCI_CBEn       (PCI_CBEn),
        .ST_FRAME       (ST_FRAME),
        .PCI_IRDYn      (PCI_IRDYn),
        .PCI_TRDYn      (CFG_TRDYn),
        .CONFIG_READ    (CONFIG_READ),
        .CONFIG_WRITE   (CONFIG_WRITE),
        .CFG_DATA_out   (CFG_DATA_out),
        .IO_EN          (IO_EN),
        .MEM_EN         (MEM_EN),
        .BUS_MASTER_EN  (BUS_MASTER_EN),
        .BASE_ADDR0     (BASE_ADDR0),
        .BASE_ADDR1     (BASE_ADDR1),
        .INT0n          (DEV0_INTn),
        .INT1n          (DEV1_INTn)
    );
    
    CFG_Target CFG_TARGET(
        .PCI_CLK        (PCI_CLK),
        .PCI_RESETn     (PCI_RESETn),
        .PCI_FRAMEn     (PCI_FRAMEn),
        .PCI_IRDYn      (PCI_IRDYn),
        .TYPE0R         (TYPE0R),
        .TYPE0W         (TYPE0W),
        .CONFIG_READ    (CONFIG_READ),
        .CONFIG_WRITE   (CONFIG_WRITE),
        .CFG_AD_OE      (CFG_AD_OE),
        .CFG_DTS_OE     (CFG_DTS_OE),
        .CFG_DEVSELn    (CFG_DEVSELn),
        .CFG_TRDYn      (CFG_TRDYn),
        .CFG_STOPn      (CFG_STOPn)
    );
    
    wire         MEM_DEVSELn;
    wire         MEM_TRDYn;
    wire         MEM_STOPn;
    wire         MEM_DTS_OE;
    wire         MEM_AD_OE;
    wire  [31:0] MEMR_Data_out;
    MEM_Target MEM_TARGET(
        .PCI_CLK        (PCI_CLK),
        .PCI_RESETn     (PCI_RESETn),
        .PCI_FRAMEn     (PCI_FRAMEn),
        .PCI_IRDYn      (PCI_IRDYn),
        .PCI_AD_in      (PCI_AD_in),
        .MEMR           (MEMR),
        .MEMW           (MEMW),
        .BK_DATA_in     (BK_DATA_in),
        .MEM_DEVSELn    (MEM_DEVSELn),
        .MEM_TRDYn      (MEM_TRDYn),
        .MEM_STOPn      (MEM_STOPn),
        .MEM_DTS_OE     (MEM_DTS_OE),
        .MEM_AD_OE      (MEM_AD_OE),
        .MEMR_Data_out  (MEMR_Data_out),
        .BK_DATA_out    (BK_DATA_out),
        .BK_EN          (BK_EN),
        .BK_RWn         (BK_RWn),
        .BK_CS0         (BK_CS0),
        .BK_CS1         (BK_CS1),
        .BA0_HIT        (BA0_HIT),
        .BA1_HIT        (BA1_HIT)
    );
    
    wire [31:0] PCI_AD_out; 
    reg         PAR_OE;
    wire        PAR_out;
    pargen PAR_GEN(
        .PCI_CLK        (PCI_CLK),
        .PCI_CBEn       (PCI_CBEn),
        .PCI_AD_out     (PCI_AD_out),
        .PAR_out        (PAR_out),
        .PAR_OE         (PAR_OE)
    );

  
assign PCI_AD_out = MEM_AD_OE ? MEMR_Data_out : CFG_AD_OE ? CFG_DATA_out : 32'b0;
  
assign PCI_DEVSELn = MEM_DTS_OE ? MEM_DEVSELn : CFG_DTS_OE ? CFG_DEVSELn : 1'b1;
  
assign PCI_TRDYn = MEM_DTS_OE ? MEM_TRDYn : CFG_DTS_OE ? CFG_TRDYn : 1'b1;
  
assign PCI_STOPn = MEM_DTS_OE ? MEM_STOPn : CFG_DTS_OE ? CFG_STOPn : 1'b1;  

assign PCI_AD_OE = MEM_AD_OE || CFG_AD_OE;

// ------------------------------------------
// pci AD bus signals    
// ------------------------------------------ 
    assign PCI_AD = PCI_AD_OE ? PCI_AD_out : 32'bz;
    assign PCI_AD_in = PCI_AD;

always @ (posedge PCI_CLK, negedge PCI_RESETn)    
    if(!PCI_RESETn)
        PAR_OE <= 1'b0;
    else
        PAR_OE <= PCI_AD_OE;

    assign PCI_PAR = PAR_OE ? PAR_out : 1'bz;
    assign PAR_in = PCI_PAR;

endmodule