config_space.v

verilog开发的PCI target模块

`timescale 1ns / 1ps
/*****************************************************************************************
* Project: l2f_recoder
* File Name: config_space.v
*
* Description: This config_space contains the registers for
*		pci target configuration space. It includes
*		two parts: Defination and Addressing
*
* modification history: 
*       1.0, 2008-01-15 qipeihong([e-mail]) Written
*       1.1, 2009-02-04 qipeihong([e-mail]) Modification discription
*                Modify PCI-PCI bridge configuration space to PCI target device, 
*                add some user definition registers in configuration space
*
* Copyright: 2009-2014 ICT,CAS.
* 
*****************************************************************************************/

module config_space(
    // input
    PCI_CLK,
    PCI_RESETn,
    PCI_AD,
    PCI_CBEn,
    ST_FRAME,
    PCI_IRDYn,
    PCI_TRDYn,
    CONFIG_READ,
    CONFIG_WRITE,

    // output
	CFG_DATA_out,
    IO_EN,
    MEM_EN,
    BUS_MASTER_EN,
    BASE_ADDR0,
    BASE_ADDR1,
    INT0n,
    INT1n
    );

    // System signals
    input    PCI_CLK;
    input    PCI_RESETn;

    // input signals
    input    PCI_IRDYn;
    input    PCI_TRDYn;

    input    [31:0]   PCI_AD;
    input    [3:0]    PCI_CBEn;
    input             ST_FRAME;
    input             CONFIG_READ;
    input             CONFIG_WRITE;
    input             INT0n;
    input             INT1n;

	// output signals
    output  [31:0]  CFG_DATA_out;
    output          IO_EN;
    output          MEM_EN;
    output          BUS_MASTER_EN;
    output  [31:20] BASE_ADDR0;
    output  [31:20] BASE_ADDR1;
    

reg [31:0] ADDR;
reg [31:0] DATA;
reg [3:0] BEn;
always @ (posedge PCI_CLK or negedge PCI_RESETn) begin
    if(!PCI_RESETn) 
        ADDR <= 32'b0;
    else if(ST_FRAME)
        ADDR <= PCI_AD;
    else begin
        DATA <= PCI_AD;
        BEn <= PCI_CBEn;
    end
end

/*******************************************************
* The definitions of PCI Configuration Space registers *
* other registers that is not defined is reserved and  *
* their value is 0 when read                           *
********************************************************/

// ======================================================
// >>>>>>>>>>>> PCI Spec. Definition parts <<<<<<<<<<<<<<
// ======================================================

// -----------------------------------------------
// Offset 00H of configuration space
// Device ID = 16'h0721, Vendor ID = 16'h1313
// -----------------------------------------------
wire [31:0] CFG_00H = 32'h07211313;	

// --------------------------------------
// Offset 04H, Status and Command
// --------------------------------------
reg STATUS8;    // Master Data Parity Error
reg STATUS11;   // Signaled Target-Abort
reg STATUS13;   // Received Master-Abort
reg STATUS14;   // Signaled System Error
reg STATUS15;   // Detected Parity Error

reg COMMAND0;   // I/O Space Enable
reg COMMAND1;   // Memory Space Enable
reg COMMAND2;   // Bus Master Enable
reg COMMAND6;   // Parity Error Response
reg COMMAND8;   // SERR# Enable

wire [31:0] CFG_04H = {STATUS15, STATUS14, STATUS13, 1'b0, STATUS11, 2'b01, STATUS8, 8'b0,		
                    7'b0, COMMAND8, 1'b0, COMMAND6, 3'b0, COMMAND2, COMMAND1, COMMAND0};		

// ----------------------------------------------------------
// Class Code = 24'h0C0500 and Revision ID = 8'h00
// ----------------------------------------------------------
wire [31:0] CFG_08H = 32'h0C050000;	

// ---------------------------------------------------------------------------
// Offset 0CH, BIST, Header Type, Latency Timer and Cache Line Size
// BIST(8'b0), Header Type(8'b0), Cache Line Size(8'b0),leaving the bottom
// three of Latency Timer as read-only, resulting in a timer granularity of
// eight clocks, consult to PCI Local Bus Spec. for more details
// ---------------------------------------------------------------------------
reg [7:3] LATENCY_TIMER_7_3;    // Latency Timer 7 to 3 bits

wire[31:0] CFG_0CH = {8'b0, 8'b0, LATENCY_TIMER_7_3, 3'b0, 8'b0};

// ----------------------------------------------------------
// Base Address Register 0 and Base Address Register 1
// ----------------------------------------------------------
reg [31:20] BA0;    // 1M memory space for device 0
reg [31:20] BA1;    // 1M memory space for device 1
wire [31:0] CFG_10H = {BA0, 20'b0};
wire [31:0] CFG_14H = {BA1, 20'b0};

// -------------------------------------------------------------
// Offset 2CH, 
// Subsystem ID = 16'h0721 and Subsystem Vendor ID = 16'h1313
// -------------------------------------------------------------
wire [31:0] CFG_2CH = 32'h07211313;

// ----------------------------------
// Offset 34H, Capabilities pointer 
// ----------------------------------
parameter [7:0] CAP_POINTER = 8'h00; 
wire [31:0] CFG_34H = {24'b0, CAP_POINTER};

// ----------------------------------------
// Offset 38H, Expansion ROM Base Address
// ----------------------------------------
wire [31:0] CFG_38H = 32'b0;

// --------------------------------------------------
// offset 3Ch of configration space, it contains
// 	1. Interrupt Line register(R, 8'h01)
//	2. Interrupt Pin register(R/W)
//	3. Min_Gnt register(R, 8'b0)
//  4. Max_Lat register(R, 8'b0)
// --------------------------------------------------
parameter [7:0] INT_PIN = 8'h01;    // Single function, only uses INTA#
reg [7:0] INT_LINE;	
	
wire [31:0] CFG_3CH = {8'b0, 8'b0, INT_PIN, INT_LINE};

// ======================================================
// >>>>>>>>>>>>>> User Definition parts <<<<<<<<<<<<<<<<<
// ======================================================

// ----------------------------------------------------
// Offset 40h, interrupt registers to indicates
// which devices occur interrupt
// ----------------------------------------------------
reg [7:0] DEV0_INT;
reg [7:0] DEV1_INT;
wire CFG_40H = {16'b0, DEV1_INT, DEV0_INT};

// -------------------------------------
// Offset 44h, error address register
// -------------------------------------
reg [31:0] CFG_44H;

// -------------------------------------
// Offset 48h, error data register
// -------------------------------------
reg [31:0] CFG_48H;

// ------------------------------------
// Offset 4Ch, error status register
// ------------------------------------
reg ADDR_PAR_ERROR;
reg DATA_PAR_ERROR;
reg ADDR_OVER_ERROR;
wire [31:0] CFG_4CH = {29'b0, ADDR_OVER_ERROR, DATA_PAR_ERROR, ADDR_PAR_ERROR};

/*******************************************************
*               The end of declaration                 *
********************************************************/

assign IO_EN = COMMAND0;
assign MEM_EN = COMMAND1;
assign BUS_MASTER_EN = COMMAND2;
assign BASE_ADDR0 = BA0;
assign BASE_ADDR1 = BA1;

// ==============================================
// configuration space addressing 
// the following code is the write operation
// to config space
// ==============================================
always @ (posedge PCI_CLK or negedge PCI_RESETn)
begin
    if(!PCI_RESETn) begin
        STATUS8 <= 1'b0; 
        STATUS11 <= 1'b0; 
        STATUS13 <= 1'b0; 
        STATUS14 <= 1'b0; 
        STATUS15 <= 1'b0;
        COMMAND0 <= 1'b0; 
        COMMAND1 <= 1'b0; 
        COMMAND2 <= 1'b0; 
        COMMAND6 <= 1'b0; 
        COMMAND8 <= 1'b0;
        LATENCY_TIMER_7_3 <= 5'b0;
        BA0 <= 12'b0;
        BA1 <= 12'b0;
        INT_LINE <= 8'b0;
        DEV0_INT <= 8'b0;
        DEV1_INT <= 8'b0;
        CFG_44H <= 32'b0;
        CFG_48H <= 32'b0;
        ADDR_PAR_ERROR <= 1'b0;
        DATA_PAR_ERROR <= 1'b0;
        ADDR_OVER_ERROR <= 1'b0;
    end
	else begin
        if(CONFIG_WRITE & !PCI_IRDYn & !PCI_TRDYn) begin
            case(ADDR[7:2])    // synopsys parallel_case full_case
                'h01: begin    // 04h  Status and Command registers
                    if(!BEn[0]) begin
                        COMMAND0 <= DATA[0];    // I/O Access Enable
                        COMMAND1 <= DATA[1];    // Memory Access Enable
                        COMMAND2 <= DATA[2];    // Bus Master Enable
                        COMMAND6 <= DATA[6];    // Parity Error Response
                    end
                    if(!BEn[1])
                        COMMAND8 <= DATA[8];	// SERR# Enable
                    if(!BEn[3]) begin
                    // -----------------------------------------
                    // These bits once set, they remain
                    // set until they are reset by writing a
                    // 1 to these bits locations
                    // -----------------------------------------
                        if(DATA[24])
                            STATUS8 <= 1'b0;    // Master Data Parity Error
                        if(DATA[27])
                            STATUS11 <= 1'b0;   // Signaled Target-Abort
                        if(DATA[29])
                            STATUS13 <= 1'b0;   // Received Master-Abort
                        if(DATA[30])
                            STATUS14 <= 1'b0;   // Signaled System Error
                        if(DATA[31])
                            STATUS15 <= 1'b0;   // Detected Parity Error
                    end	
                end

                'h03: begin    // 0Dh, Latendy Timer's upper 5 bits
                    if(!BEn[1])
                        LATENCY_TIMER_7_3 <= DATA[15:11];
                end

                'h04: begin    // 10h, Base address register for memory
                    if(!BEn[2])
                        BA0[23:20] <= DATA[23:20];
                    if(!BEn[3])
                        BA0[31:24] <= DATA[31:24];
                end

                'h05: begin    // 14h, Base address register for memory
                    if(!BEn[2])
                        BA1[23:20] <= DATA[23:20];
                    if(!BEn[3])
                        BA1[31:24] <= DATA[31:24];
                end

                'h0F: begin     // 3Ch, Interrupt line registers
                    if(!BEn[0])
                        INT_LINE <= DATA[7:0];
                end

                'h10: begin
                    if(!BEn[0])
                        DEV0_INT <= DATA[7:0];
                    if(!BEn[1])
                        DEV1_INT <= DATA[15:8];
                end
                
                default: ;

            endcase
        end
        else begin
            if(!INT0n)
                DEV0_INT <= 8'h01;  // set device 0 interrupt register
            if(!INT1n)
                DEV1_INT <= 8'h01;  // set device 1 interrupt register
        end
       
    end    // end of else	
end	   // end of always


reg [31:0] CFG_DATA_out;

parameter [1:0]
    SM_IDLE = 2'b01,
    SM_CFGR = 2'b10;

reg [1:0] CState;   // current state
reg [1:0] NState;   // next state
always @ (posedge PCI_CLK or negedge PCI_RESETn) begin
    if(!PCI_RESETn)
        CState <= SM_IDLE;
    else
        CState <= NState;
end

// ----------------------------------------------
// the following code is the read operation
// for config space
// ----------------------------------------------
always @ * begin
    if(!PCI_RESETn) begin
        NState = SM_IDLE;
        CFG_DATA_out = 32'b0;
    end
    else begin
        NState = CState;
        case (CState)	// synopsys parallel_case full_case
            SM_IDLE: begin
                CFG_DATA_out = 32'b0;
                if(CONFIG_READ)
                    NState = SM_CFGR;
                else
                    NState = SM_IDLE;
            end

            SM_CFGR: begin
                if(!PCI_IRDYn & !PCI_TRDYn) begin
                    case(ADDR[7:2])    // synopsys parallel_case full_case
                        'h00:
                            CFG_DATA_out = CFG_00H;
                        'h01:
                            CFG_DATA_out = CFG_04H;
                        'h02:
                            CFG_DATA_out = CFG_08H;
                        'h03:
                            CFG_DATA_out = CFG_0CH;
                        'h04:
                            CFG_DATA_out = CFG_10H;
                        'h05:
                            CFG_DATA_out = CFG_14H;
                        'h0B:
                            CFG_DATA_out = CFG_2CH;
                        'h0F:
                            CFG_DATA_out = CFG_3CH;
                        'h10:
                            CFG_DATA_out = CFG_40H;
                        'h11:
                            CFG_DATA_out = CFG_44H;
                        'h12:
                            CFG_DATA_out = CFG_48H;
                        'h13:
                            CFG_DATA_out = CFG_4CH;
                        default:
                            CFG_DATA_out = 32'h00000000;    // CFG_DATA_out
                    endcase
                end	
                else if(!CONFIG_READ)
                    NState = SM_IDLE;					
            end	

            default:
                NState = SM_IDLE;
        endcase
    end    // end of else
end

endmodule