pargen.v

来自「verilog开发的PCI target模块」· Verilog 代码 · 共 81 行

`timescale 1ns / 1ps
/*************************************************************
* Project Name: l2f_recoder
* File Name: par.v
*
* Description: This module is used to generate the
*		PAR signal when read data phase, also it
*		can check parity during address and write data phase
*
* modification history:
*       1.0, 2008-03-24, qipeihong([e-mail]) Written
*
* Copyright: 2009-2014 ICT,CAS.
* 
**************************************************************/
// ----------------------------------------------------------
// history:
// ----------------------------------------------------------

module pargen(
    PAR_out, 
    PCI_CBEn, 
    PCI_AD_out, 
    PCI_CLK, 
    PAR_OE
);

  output PAR_out;
  input [3:0] PCI_CBEn;
  input [31:0] PCI_AD_out;
  input PCI_CLK;
  input PAR_OE;
  
 reg cbe_reg;
 reg par3, par2, par1, par0;
 reg par_reg;
 
// Not ALL synthesis tools create an optimal parity circuit, 
// so an SOP (Sum Of Products) equivalent of the following 
// assignment is used.
// assign #2 PAR_out = ^{par3,par2,par1,par0,cbe_reg}; // 2^5-1=16PT's so 1 Tpd


// Special Parity block that works with all synthesis tools

 assign #2 PAR_out = par_reg;
 
 always @ (par3 or par2 or par1 or par0 or cbe_reg) begin 
    case ({par3, par2, par1, par0, cbe_reg})
       5'b00001: par_reg =  1;
       5'b00010: par_reg =  1;
       5'b00100: par_reg =  1;
       5'b00111: par_reg =  1;
       5'b01000: par_reg =  1;
       5'b01011: par_reg =  1;
       5'b01101: par_reg =  1;
       5'b01110: par_reg =  1;
       5'b10000: par_reg =  1;
       5'b10011: par_reg =  1;
       5'b10101: par_reg =  1;
       5'b10110: par_reg =  1;
       5'b11001: par_reg =  1;
       5'b11010: par_reg =  1;
       5'b11100: par_reg =  1;
       5'b11111: par_reg =  1;
       default: par_reg =  0;
    endcase
    
   end

 always @ (posedge PCI_CLK) begin 
    if (PAR_OE == 1'b1) begin 
        par3 <= #1 ^PCI_AD_out[31:24]; // 2 Tpdi's
        par2 <= #1 ^PCI_AD_out[23:16];
        par1 <= #1 ^PCI_AD_out[15:8];
        par0 <= #1 ^PCI_AD_out[7:0];
        cbe_reg <= #1 ^PCI_CBEn[3:0];
    end
   end
 
endmodule //of pargen