cfg_target.v

verilog开发的PCI target模块

`timescale 1ns / 1ps
/*************************************************************
* Project Name: L2F_Recoder
* File Name: CFG_Target.v
*
* Description: This config target module is used to generate
*		the DEVSEL#, TRDY# and STOP# signals when PCI bus
*		initializes a type0 transaction, also it provides signals
*       to the config_space module
*
* Company : ICT
* Author: qipeihong([e-mail])
* Tool versions:  Xilinx ISE 9.2i
* Create Date: 2008-03-15
* Revision 0.01 - File Created
*
* Additional Comments:
* 
**************************************************************/
// ----------------------------------------------------------
// history:
// ----------------------------------------------------------

module CFG_Target(
    PCI_CLK,
    PCI_RESETn,
    PCI_IRDYn,
    PCI_FRAMEn,
    TYPE0R,
    TYPE0W,
    CFG_DEVSELn,
    CFG_STOPn,
    CFG_TRDYn,
    CFG_DTS_OE,
    CFG_AD_OE,
    CONFIG_READ,
    CONFIG_WRITE
);

// -----------------------------------
//          PCI Interface
// -----------------------------------
        input           PCI_CLK;        // system clock
        input           PCI_RESETn;     // system reset
        input           PCI_IRDYn;      // primary bus IRDY#
        input           PCI_FRAMEn;     // from DEC
//      input           ST_FRAME;       // from DEC
        output          CFG_DEVSELn;
        output          CFG_TRDYn;
        output          CFG_STOPn;
        output          CFG_DTS_OE;     // Output Enable for DEVSELn, TRDYn, STOPn(DTS)
        output          CFG_AD_OE;      // Output Enable for AD bus
		
// -----------------------------------
//          backend signals
// -----------------------------------
        input           TYPE0R;
        input           TYPE0W;
        output          CONFIG_READ;
        output          CONFIG_WRITE;
	
// definition of state machine
parameter [5:0]
    IDLE = 6'b00_0001,       // 1
    WAIT = 6'b00_0010,       // 2
    CON = 6'b00_0100,        // 4 
    ABORT = 6'b00_1000,      // 8
    BACKOFF = 6'b01_0000,    // 16
    DISCON = 6'b10_0000;
reg [5:0]   CState;
reg [5:0]   NState;

reg     CFG_DEVSELn;
reg     CFG_STOPn;
reg     CFG_TRDYn;
reg     CFG_AD_OE;
reg     CFG_DTS_OE;

always @ (posedge PCI_CLK, negedge PCI_RESETn) begin
    if(!PCI_RESETn)
        CState <= IDLE;
    else
        CState <= NState;
end

always @ * begin
    case(CState)	// synopsys parallel_case full_case
        IDLE: begin
            if(TYPE0R | TYPE0W)
                NState = WAIT;
            else
                NState = IDLE;
        end

        WAIT: begin
            NState = CON;
        end

        CON: begin
            if(!PCI_FRAMEn & !PCI_IRDYn)
                NState = DISCON;
            // --------------------------------------
            // when the master isn't ready, stay in
            // the current state
            // --------------------------------------
            else if(!PCI_FRAMEn & PCI_IRDYn)
                NState = CON;
            // ----------------------------------------------
            // when the master abort, back to the IDLE state
            // ----------------------------------------------
            else if(PCI_FRAMEn & PCI_IRDYn)
                NState = BACKOFF;
            // ------------------------------------------
            // one data transaction, go to BACKOFF state
            // ------------------------------------------
            else if(PCI_FRAMEn & !PCI_IRDYn) 
                NState = BACKOFF;
            else
                NState = BACKOFF;
        end

        BACKOFF: begin
            NState = IDLE;
        end

        DISCON: begin
            if(PCI_FRAMEn)
                NState = IDLE;
            else
                NState = DISCON;
        end
        
        default: begin
            NState = IDLE;
        end

    endcase
    
end

reg CONFIG_READ, CONFIG_WRITE;
always @ (posedge PCI_CLK, negedge PCI_RESETn) begin
    if(!PCI_RESETn) begin
        CFG_DEVSELn <= 1'b1;
        CFG_STOPn <= 1'b1;
        CFG_TRDYn <= 1'b1;
        CFG_AD_OE <= 1'b0;
        CFG_DTS_OE <= 1'b0;
        CONFIG_READ <= 1'b0;
        CONFIG_WRITE <= 1'b0;
    end
    else begin
        case(CState)    // synopsys parallel_case full_case
            IDLE: begin	    // IDLE, wait the config read/write
                CFG_DEVSELn <= #1 1'b1;
                CFG_STOPn <= #1 1'b1;
                CFG_TRDYn <= #1 1'b1;
                CFG_AD_OE <= #1 1'b0;
                CFG_DTS_OE <= #1 1'b0;
                if(TYPE0R) begin
                    CONFIG_READ <= #1 1'b1;
                    CONFIG_WRITE <= #1 1'b0;
                end
                else if(TYPE0W) begin
                    CONFIG_READ <= #1 1'b0;
                    CONFIG_WRITE <= #1 1'b1;
                end
            end

            WAIT: begin
                CFG_DEVSELn <= #1 1'b0;
                CFG_DTS_OE <= #1 1'b1;
                if(CONFIG_READ)
                    CFG_AD_OE <= #1 1'b1;
                else
                    CFG_AD_OE <= #1 1'b0;
            end

            CON: begin   // config read or write
                // -------------------------------------
                // only support single transaction, so
                // when multi transaction, assert STOP#
                // to stop the current transaction, 
                // disconnect with data
                // -------------------------------------
                if(!PCI_FRAMEn & !PCI_IRDYn) begin
                    CFG_STOPn <= #1 1'b0;
                    CFG_TRDYn <= #1 1'b0;
                end
                // --------------------------------------
                // when the master isn't ready, stay in
                // the current state
                // --------------------------------------
                else if(!PCI_FRAMEn & PCI_IRDYn) begin
                    CFG_STOPn <= #1 1'b1;
                    CFG_TRDYn <= #1 1'b0;
                end 
                // ----------------------------------------------
                // when the master abort, back to the IDLE state
                // ----------------------------------------------
                else if(PCI_FRAMEn & PCI_IRDYn) begin
                    CFG_DEVSELn <= #1 1'b1;
                    CFG_TRDYn <= #1 1'b1;
                end
                // ------------------------------------------
                // one data transaction, go to BACKOFF state
                // ------------------------------------------
                else if(PCI_FRAMEn & !PCI_IRDYn) begin
                    CFG_TRDYn <= #1 1'b0;
                end
                else begin
                    CFG_DEVSELn <= #1 1'b1;
                    CFG_STOPn <= #1 1'b1;
                    CFG_TRDYn <= #1 1'b1;
                    CFG_AD_OE <= #1 1'b0;
                end
            end

            BACKOFF: begin		// prepare to release the bus
                CFG_DEVSELn <= #1 1'b1;
                CFG_STOPn <= #1 1'b1;
                CFG_TRDYn <= #1 1'b1;
                CFG_DTS_OE <= #1 1'b0;
                CFG_AD_OE <= #1 1'b0;
                CONFIG_READ <= #1 1'b0;
                CONFIG_WRITE <= #1 1'b0;
            end

            DISCON: begin
                if(PCI_FRAMEn) begin
                    CFG_DEVSELn <= 1'b1;
                    CFG_STOPn <= 1'b1;
                    CFG_TRDYn <= 1'b1;
                    CFG_DTS_OE <= 1'b0;
                    CFG_AD_OE <= 1'b0;
                    CONFIG_READ <= 1'b0;
                    CONFIG_WRITE <= 1'b0;
                end
                else begin
                    CFG_DEVSELn <= 1'b0;
                    CFG_TRDYn <= 1'b1;
                    CFG_STOPn <= 1'b1;
                end
            end
            
            default: begin		// the default state is IDLE
                CFG_DEVSELn <= #1 1'b1;
                CFG_STOPn <= #1 1'b1;
                CFG_TRDYn <= #1 1'b0;
                CFG_AD_OE <= #1 1'b0;
                CFG_DTS_OE <= #1 1'b0;
                CONFIG_READ <= #1 1'b0;
                CONFIG_WRITE <= #1 1'b0;
            end
        endcase
    end
end
endmodule