ep1c6_32_vga.tan.rpt

来自「VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 」· RPT 代码 · 共 288 行 · 第 1/5 页

Timing Analyzer report for ep1c6_32_vga
Sun Dec 28 20:28:31 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'pll:U1|altpll:altpll_component|_clk0'
  6. Clock Hold: 'pll:U1|altpll:altpll_component|_clk0'
  7. tco
  8. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                       ;
+-----------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------+--------------+--------------------------------------+--------------------------------------+--------------+
; Type                                                ; Slack     ; Required Time                    ; Actual Time                      ; From      ; To           ; From Clock                           ; To Clock                             ; Failed Paths ;
+-----------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------+--------------+--------------------------------------+--------------------------------------+--------------+
; Worst-case tco                                      ; N/A       ; None                             ; 13.600 ns                        ; vcount[5] ; disp_dato[2] ; clock                                ; --                                   ; 0            ;
; Clock Setup: 'pll:U1|altpll:altpll_component|_clk0' ; 33.493 ns ; 25.00 MHz ( period = 40.000 ns ) ; 153.68 MHz ( period = 6.507 ns ) ; vcount[5] ; timer[1]     ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'pll:U1|altpll:altpll_component|_clk0'  ; 0.499 ns  ; 25.00 MHz ( period = 40.000 ns ) ; N/A                              ; timer[0]  ; timer[0]     ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                        ;           ;                                  ;                                  ;           ;              ;                                      ;                                      ; 0            ;
+-----------------------------------------------------+-----------+----------------------------------+----------------------------------+-----------+--------------+--------------------------------------+--------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP2C8Q208C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;