ep1c6_32_vga.tan.rpt

来自「VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 」· RPT 代码 · 共 288 行 · 第 1/5 页

; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; On                 ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; On                 ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                    ;
+--------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name                      ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+--------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; pll:U1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 25.0 MHz         ; -2.388 ns     ; -2.388 ns    ; clock    ; 5                     ; 2                   ; AUTO   ;              ;
; clock                                ;                    ; User Pin   ; 10.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+--------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll:U1|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+--------------------------------------+--------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From      ; To        ; From Clock                           ; To Clock                             ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+--------------------------------------+--------------------------------------+-----------------------------+---------------------------+-------------------------+
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[1]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[2]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[3]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[4]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[5]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[6]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[7]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[8]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.493 ns                               ; 153.68 MHz ( period = 6.507 ns )                    ; vcount[5] ; timer[9]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.245 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[1]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[2]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[3]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[4]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[5]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[6]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[7]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[8]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.658 ns                               ; 157.68 MHz ( period = 6.342 ns )                    ; vcount[4] ; timer[9]  ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.738 ns                 ; 6.080 ns                ;
; 33.838 ns                               ; 162.28 MHz ( period = 6.162 ns )                    ; vcount[5] ; vcount[3] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 5.898 ns                ;
; 33.839 ns                               ; 162.31 MHz ( period = 6.161 ns )                    ; vcount[5] ; vcount[9] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 5.897 ns                ;
; 33.839 ns                               ; 162.31 MHz ( period = 6.161 ns )                    ; vcount[5] ; vcount[0] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 5.897 ns                ;
; 33.913 ns                               ; 164.28 MHz ( period = 6.087 ns )                    ; vcount[5] ; vcount[2] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.739 ns                 ; 5.826 ns                ;
; 34.003 ns                               ; 166.75 MHz ( period = 5.997 ns )                    ; vcount[4] ; vcount[3] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 5.733 ns                ;
; 34.004 ns                               ; 166.78 MHz ( period = 5.996 ns )                    ; vcount[4] ; vcount[9] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 5.732 ns                ;
; 34.004 ns                               ; 166.78 MHz ( period = 5.996 ns )                    ; vcount[4] ; vcount[0] ; pll:U1|altpll:altpll_component|_clk0 ; pll:U1|altpll:altpll_component|_clk0 ; 40.000 ns                   ; 39.736 ns                 ; 5.732 ns                ;