clk_generator.vhd

来自「采用VHDL语言编写的万年历程序」· VHDL 代码 · 共 52 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clk_generator is
    Port ( clk : in std_logic;
           clk_1Hz : out std_logic;
           clk_statemachine : out std_logic;
			  pulse   :out std_logic);
end clk_generator;

architecture Behavioral of clk_generator is

begin
    process(clk)
	    variable m,l:integer range 0 to 50000000;
		 variable n:integer range 0 to 5000;
	 begin
		 if rising_edge(clk)then
		    if l=50000000 then
			    l:=0;
			 end if;
          if n=50000000 then
			    n:=0;
			 end if;
			 if m=24000000 then
			    m:=0;
			 end if;
			 if l<=25000000 then
			    pulse<='0';
			 else
			    pulse<='1';
			 end if;
			 if n<=2500 then
				 clk_1Hz<='1';
			 else 
      	    clk_1Hz<='0';
			 end if;
			 if m<=12000000 then
			    clk_statemachine<='1';
			 else
			    clk_statemachine<='0';
			 end if;
			 l:=l+1;
			 n:=n+1;
			 m:=m+1;
		 end if;
	 end process;

end Behavioral;