wannianli.npl

采用VHDL语言编写的万年历程序

JDF E
// Created by ISE ver 1.0
PROJECT wannianli
DESIGN wannianli Normal
DEVKIT xc2s100-5pq208
DEVFAM spartan2
FLOW XST VHDL
STIMULUS 3.tbw Normal
STIMULUS dd.tbw Normal
MODULE Counter.vhd
MODSTYLE counter Normal
MODULE date_counter.vhd
MODSTYLE date_counter Normal
MODULE Minute.vhd
MODSTYLE minute Normal
MODULE gate_and2.vhd
MODSTYLE gate_and2 Normal
MODULE comperator.vhd
MODSTYLE comparator Normal
MODULE Hour.vhd
MODSTYLE hour Normal
MODULE data_send.vhd
MODSTYLE data_send Normal
MODULE clk_generator.vhd
MODSTYLE clk_generator Normal
MODULE Second.vhd
MODSTYLE second Normal
MODULE Clock.vhd
MODSTYLE clock Normal
MODULE statemachine.vhd
MODSTYLE statemachine Normal
MODULE ssend.vhd
MODSTYLE ssend Normal
MODULE top_date_clock.vhd
MODSTYLE top_date_clock Normal
MODULE key.vhd
MODSTYLE key Normal

[STRATEGY-LIST]
Normal=True, 1189324338

[Normal]
xilxBitgStart_Clk=xstvhd, SPARTAN2, Implementation.t_bitFile, 1189326321, JTAG Clock