comperator.vhd

采用VHDL语言编写的万年历程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is
    Port ( dayh : in std_logic_vector(3 downto 0);
           dayl : in std_logic_vector(3 downto 0);
           hourh : in std_logic_vector(3 downto 0);
           hourl : in std_logic_vector(3 downto 0);
			  minutel:in std_logic_vector(3 downto 0);
			  minuteh:in std_logic_vector(3 downto 0);
           input_dayh : in std_logic_vector(3 downto 0);
           input_dayl : in std_logic_vector(3 downto 0);
           input_hourh : in std_logic_vector(3 downto 0);
           input_hourl : in std_logic_vector(3 downto 0);
			  input_minuteh : in std_logic_vector(3 downto 0);
           input_minutel : in std_logic_vector(3 downto 0);
           count_hours : in std_logic_vector(7 downto 0);
           output_star : out std_logic);
end comparator;

architecture Behavioral of comparator is
signal temp1,temp2,temp3:integer;
begin
  comparator:process(dayh,dayl,hourh,hourl,minuteh,minutel,input_dayh,input_dayl,input_hourh,input_minuteh,input_minutel,input_hourl)
	          begin
				    temp1<=conv_integer(minutel)+conv_integer(minuteh)*10+conv_integer(hourl)*60+conv_integer(hourh)*600+conv_integer(dayl)*24*60+conv_integer(dayh)*240*60;
					 temp2<=conv_integer(input_minutel)+conv_integer(input_minuteh)*10+conv_integer(input_hourl)*60+conv_integer(input_hourh)*600+conv_integer(input_dayl)*24*60+conv_integer(input_dayh)*240*60;
					 temp3<=conv_integer(input_minutel)+conv_integer(input_minuteh)*10+conv_integer(input_hourl)*60+conv_integer(input_hourh)*600+conv_integer(input_dayl)*24*60+conv_integer(input_dayh)*240*60+conv_integer(count_hours(3 downto 0))*60+conv_integer(count_hours(7 downto 4))*600;
	          end process;
  counter:   process(temp1,temp2,temp3)
             begin
				    if temp1>=temp2 and temp1<temp3 then
					    output_star<='1';
				    else
					    output_star<='0';
					 end if;
				 end process;
end Behavioral;