📄 key.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity key is
Port (sysclk,key1,reset,add,sub: in std_logic;
led1,led10,led100,led1000,clock3200: out std_logic;
N:out integer range 1023 downto 0);
end key;
architecture Behavioral of key is
type state is (st1,st2);
signal current :state;
type state_1 is (s1,s2,s3);
signal current_1 :state_1;
signal clk3200:std_logic;
signal step1,step10,step100,step1000 :std_logic;
begin
process(sysclk,reset)
variable count2: integer;
variable clk0: std_logic;
begin
if reset='0' then
count2:=0;
clk0:='0';
elsif sysclk'event and sysclk='1' then
count2:=count2+1;
if count2=1600 then
clk0:='1';
elsif count2=3200 then
count2:=0;
clk0:='0';
--end if;
end if;
end if;
clock3200<=clk0;
clk3200<=clk0;
end process;
process(key1,clk3200)
variable cnt :integer range 4 downto 0 ;
begin
if reset='0' then
cnt:=0;
current<=st1;
step1<='1';step10<='1';step100<='0';step1000<='1';
elsif rising_edge(clk3200) then
case current is
when st1 =>if key1='0' then current<=st2;
end if;
when st2 =>if key1='1' then
cnt:=cnt+1;
case cnt is
when 1=>step1<='0';step10<='1';step100<='1';step1000<='1';current<=st1;
when 2=>step1<='1';step10<='0';step100<='1';step1000<='1';current<=st1;
when 3=>step1<='1';step10<='1';step100<='0';step1000<='1';current<=st1;
when 4=>step1<='1';step10<='1';step100<='1';step1000<='0';cnt:=0;current<=st1;
when others =>null;
end case;
end if;
when others=>null;
end case;
end if;
end process;
process(reset,clk3200)
variable count2,count3,count5: integer range 1023 downto 0 ;
variable clk0: std_logic;
begin
if reset='0' then
N<=100;
clk0:='0';
count3:=100;
current_1<=s1;
elsif clk3200'event and clk3200='1' then
case current_1 is
when s1 =>if add='0' then current_1<=s2;
elsif sub='0' then current_1<=s3;
end if;
when s2 =>if add='1' then
if step1='0' then count3:=count3+1;current_1<=s1;
elsif step10='0' then count3:=count3+10;current_1<=s1;
elsif step100='0' then count3:=count3+100;current_1<=s1;
elsif step1000='0' then count3:=count3+1000;current_1<=s1;
end if;
end if;
when s3 =>if sub='1' then
if step1='0' then count3:=count3-1;current_1<=s1;
elsif step10='0' then count3:=count3-10;current_1<=s1;
elsif step100='0' then count3:=count3-100;current_1<=s1;
elsif step1000='0' then count3:=count3-1000;current_1<=s1;
end if;
end if;
when others =>null;
end case;
end if;
N<=count3;
end process ;
led1<=step1;led10<=step10;led100<=step100;led1000<=step1000;
end Behavioral;
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