hour.vhd

采用VHDL语言编写的万年历程序

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--This module is uesed as a 24 counter,when count to 24 it will automatically back to 00,  --
--and the carry will be '1' to drive day-counter.                                          --
--Pay attention here: carry will hold '1' for 1 hour,form 00-01 hour.                      --
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hour is
    Port ( clk_minute : in std_logic;
	        reset:in std_logic;
			  --start:in std_logic;
			  set_hour:in std_logic_vector(7 downto 0);
           carry : out std_logic;
			  out1:out std_logic_vector(7 downto 0));--BCD code output,0--24;
end hour;

architecture Behavioral of hour is

begin
     process(clk_minute,reset,set_hour)
	     variable n:std_logic_vector(out1'left downto out1'right);
 		  variable m:integer range 0 to 16;
	  begin
	     if reset='0'then
		     out1<=set_hour;          --preset the hour;
			  carry<='0';
			  n:=set_hour;
			  m:=conv_integer(set_hour(set_hour'right+3 downto 0));--n,m must be modified at the same time;
		  elsif rising_edge(clk_minute)then
		     --if start='0'then
		        n:=n+1;
			     m:=m+1;   		     			  
			     if m=10 then             --m=10 means n="1001";
			        n:=n+"00000110";      --Because of using BCD code,so if n="1001",n=n+6;
				     m:=0;
			     end if;
			     if n="00100100"then      --when n=24 hour; 
			        n:="00000000";
				     m:=0;
				     carry<='1';
              else
			        carry<='0';
			     end if;			  
			     out1<=n;
		     --end if;
		  end if;
	  end process;
end Behavioral;