📄 lcd_driver.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity lcd_driver is
generic(N:integer:=3200;
delay:integer:=100);
Port ( clk : in std_logic;
reset:in std_logic;
flash:in integer range 0 to 31;
year_h : in std_logic_vector(7 downto 0);
year_mh : in std_logic_vector(7 downto 0);
year_ml : in std_logic_vector(7 downto 0);
year_l : in std_logic_vector(7 downto 0);
month_h : in std_logic_vector(7 downto 0);
month_l : in std_logic_vector(7 downto 0);
day_h : in std_logic_vector(7 downto 0);
day_l : in std_logic_vector(7 downto 0);
hour_h : in std_logic_vector(7 downto 0);
hour_l : in std_logic_vector(7 downto 0);
minute_h : in std_logic_vector(7 downto 0);
minute_l : in std_logic_vector(7 downto 0);
second_h : in std_logic_vector(7 downto 0);
second_l : in std_logic_vector(7 downto 0);
count_dayh : in std_logic_vector(7 downto 0);
count_dayl : in std_logic_vector(7 downto 0);
count_hourh : in std_logic_vector(7 downto 0);
count_hourl: in std_logic_vector(7 downto 0);
count_minuteh: in std_logic_vector(7 downto 0);
count_minutel : in std_logic_vector(7 downto 0);
how_many_hourh : in std_logic_vector(7 downto 0);
how_many_hourl : in std_logic_vector(7 downto 0);
resulth:in std_logic_vector(7 downto 0);
resultmh:in std_logic_vector(7 downto 0);
resultml:in std_logic_vector(7 downto 0);
resultl:in std_logic_vector(7 downto 0);
lcdda : out std_logic;
lcdrw : out std_logic;
lcden : out std_logic;
data : inout std_logic_vector(7 downto 0));
end lcd_driver;
architecture Behavioral of lcd_driver is
type state is (set_dlnf,clear_lcd,set_cursor,set_dcb,set_location,write_data,set_location2,write_data2);
signal current_state:state;
type ram is array(0 to 31) of std_logic_vector(7 downto 0);
signal dataram :ram;
signal clkk:std_logic;
begin
loaddata:process(clk,reset)
begin
if rising_edge(clk)then
dataram(0)<=year_h;dataram(1)<=year_mh;dataram(2)<=year_ml;
dataram(3)<=year_l;dataram(4)<=month_h;dataram(5)<=month_l;
dataram(6)<=day_h; dataram(7)<=day_l; dataram(8)<="00100000";
dataram(9)<="00100000";dataram(10)<=hour_h;dataram(11)<=hour_l;
dataram(12)<=minute_h;dataram(13)<=minute_l;dataram(14)<=second_h;
dataram(15)<=second_l;
-----------------------------
dataram(16)<=count_dayh;dataram(17)<=count_dayl;dataram(18)<=count_hourh;
dataram(19)<=count_hourl;dataram(20)<=count_minuteh;dataram(21)<=count_minutel;
dataram(22)<=how_many_hourh;dataram(23)<=how_many_hourl;dataram(24)<="00100000";
dataram(25)<="00100000";dataram(26)<="00100000";dataram(27)<="00100000";
dataram(28)<=resulth;dataram(29)<=resultmh;dataram(30)<=resultml;dataram(31)<=resultl;
end if;
end process;
divider:process(clk,reset)
variable cnt:integer;
begin
if reset='0'then
cnt:=0;
elsif rising_edge(clk)then
cnt:=cnt+1;
if cnt<=N then
clkk<='1';
else
clkk<='0';
end if;
if cnt=2*N then
cnt:=0;
end if;
end if;
end process;
controll:process(clkk,reset,current_state)
variable cntt:integer range 0 to 1000;
variable cnt2:integer range 0 to 32;
variable cnt3:std_logic_vector(5 downto 0);
begin
if reset='0'then
current_state<=set_dlnf;
cntt:=0;cnt2:=0;
elsif rising_edge(clkk)then
cnt3:=cnt3+1;
case current_state is
when set_dlnf=>
lcden<='0';
lcdda<='0';
lcdrw<='0';
data<="00111100";
cntt:=cntt+1;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=clear_lcd;
cntt:=0;
end if;
when clear_lcd=>
lcden<='0';
lcdda<='0';
lcdrw<='0';
data<="00000001";
cntt:=cntt+1;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=set_cursor;
cntt:=0;
end if;
when set_cursor=>
lcden<='0';
lcdda<='0';
lcdrw<='0';
data<="00000110";
cntt:=cntt+1;
if cntt>delay*3 and cntt<=delay*6 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*9 then
current_state<=set_dcb;
cntt:=0;
end if;
when set_dcb=>
lcden<='0';
lcdda<='0';
lcdrw<='0';
data<="00001110";
cntt:=cntt+1;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=set_location;
cntt:=0;
end if;
when set_location=>
lcden<='0';
lcdda<='0';
lcdrw<='0';
data<="10000000";
cntt:=cntt+1;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=write_data;
cntt:=0;
end if;
when write_data=>
lcden<='0';
lcdda<='1';
lcdrw<='0';
if cnt2<=15 then
data<=dataram(cnt2);
cntt:=cntt+1;
if cnt3<="010000"then
if cnt2=flash then
data<="00100000";
end if;
end if;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=write_data;
cntt:=0;
cnt2:=cnt2+1;
end if;
else
--cnt2:=0;
current_state<=set_location2;
end if;
when set_location2=>
lcden<='0';
lcdda<='0';
lcdrw<='0';
data<="11000000";
cntt:=cntt+1;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=write_data2;
cntt:=0;
end if;
when write_data2=>
lcden<='0';
lcdda<='1';
lcdrw<='0';
if cnt2<=31 then
data<=dataram(cnt2);
cntt:=cntt+1;
if cnt3<="010000"then
if cnt2=flash then
data<="00100000";
end if;
end if;
if cntt>delay and cntt<=delay*2 then--delay 200us
lcden<='1';
else --delay 200us
lcden<='0';
end if;
if cntt=delay*3 then
current_state<=write_data2;
cntt:=0;
cnt2:=cnt2+1;
end if;
else
cnt2:=0;
current_state<=set_cursor;
end if;
end case;
end if;
end process;
end Behavioral;
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