clock.vhd

采用VHDL语言编写的万年历程序

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--This top module combined 3 modules:second,minute,hour.It is used as a clock.                                      --
--Input:  clk_1Hz        ( 1Hz frequence to drive the second modules)                                               --
--        clock_reset    ( if clock_reset is '0' the port preset_second,preset_minute,preset_hour's data come in,   --
--                      and will be out throught port out_second,out_minute,out_hour,and carry will be '0',         --
--                       if clock_reset is '1' then clock is started.)                                              --
--        preset_second  ( used to preset second.For example preset_second="00100001" means 21 second)              --
--        preset_minute  ( used to preset minute)                                                                   --
--        preset_hour    ( used to preset hour)                                                                     --
--Output: out_second     ( used to output second.For example out_second="00100001" means 21 second)                 --
--        out_minute     ( used to output minute)                                                                   --
--        out_hour       ( used to output hour)                                                                     --
--        out_carry      ( carry come form hour module,if n="00100100"(24) out_carry will be '1' for 1 hour time)   --
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
    Port ( clk_1Hz:in std_logic;
	        clock_reset : in std_logic;
			  --start       : in std_logic;
           preset_second : in std_logic_vector(7 downto 0);
           preset_minute : in std_logic_vector(7 downto 0);
           preset_hour : in std_logic_vector(7 downto 0);
           out_second : out std_logic_vector(7 downto 0);
           out_minute : out std_logic_vector(7 downto 0);
           out_hour : out std_logic_vector(7 downto 0);
           out_carry : out std_logic);
end clock;

architecture Behavioral of clock is
component second
     Port ( F_1Hz : in std_logic;
	        reset : in std_logic;
			  --start       : in std_logic;
	        set_second   : in std_logic_vector(7 downto 0);
           carry : out std_logic;
			  out1:out std_logic_vector(7 downto 0));--BCD code output,0--60;
end component;
component minute
     Port ( clk_second : in std_logic;
	        reset:in std_logic;
			  --start       : in std_logic;
			  set_minute:in std_logic_vector(7 downto 0);
           carry : out std_logic;
			  out1:out std_logic_vector(7 downto 0));--BCD code output,0--60;
end component;
component hour
     Port ( clk_minute : in std_logic;
	        reset:in std_logic;
			  --start       : in std_logic;
			  set_hour:in std_logic_vector(7 downto 0);
           carry : out std_logic;
			  out1:out std_logic_vector(7 downto 0));--BCD code output,0--24;
end component;
    signal temp1,temp2,temp3:std_logic;
begin
	 u2:second  port map(F_1Hz=>clk_1Hz,reset=>clock_reset,set_second=>preset_second,carry=>temp2,out1=>out_second);
    u3:minute  port map(clk_second=>temp2,reset=>clock_reset,set_minute=>preset_minute,carry=>temp3,out1=>out_minute);
	 u4:hour    port map(clk_minute=>temp3,reset=>clock_reset,set_hour=>preset_hour,carry=>out_carry,out1=>out_hour);

end Behavioral;