second.vhd

采用VHDL语言编写的万年历程序

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--本模块用来对预置的set_second(7 downto 0)进行计数，从0到59秒，然后回0，且进位carry来高电平；reset=0时将set_second输出，carry<=0,完成初始化；--
--关于是用'left,'right,'high,'low属性的好处：使用这些属性能使已经设计好的模块更通用化，因为在再利用时可以通过改尽量少的参数而达到目的；      --
--甚至可以作到，只改动输入或输出的位数，便达到目的，这也是我们要追求的；                                                                      --
--便量m用到了integer型，这是不好的做法，希望改进成std_logic_vector型；                                                                       --          
--注意：  carry产生的高电平为1秒;                                                                                                            --        
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity second is
    Port ( F_1Hz : in std_logic;
	        reset : in std_logic;
			  --start : in std_logic;
	        set_second   : in std_logic_vector(7 downto 0);
           carry : out std_logic;
			  out1:out std_logic_vector(7 downto 0));--BCD code output,0--60;
end second;

architecture Behavioral of second is

begin
     process(F_1Hz,set_second,reset)
	     variable n:std_logic_vector(out1'left downto out1'right);
 		  variable m:integer range 0 to 16;
	  begin
	     if reset='0'then
		     out1<=set_second;        --preset the second
			  carry<='0';
			  n:=set_second;      
			  m:=conv_integer(set_second(set_second'right+3 downto 0));--n,m must be modified at the same time;
		  elsif rising_edge(F_1Hz)then
		        --if start='0'then
		           n:=n+1;
			        m:=m+1;   		     			  
			        if m=10 then             --m=10 means n="1001";
			           n:=n+"00000110";      --Because of using BCD code,so if n="1001",n=n+6;
				        m:=0;
			        end if;
			        if n="01100000"then      --when n=60 second; 
			           n:="00000000";
				        m:=0;
				        carry<='1';
                 else
			           carry<='0';
			        end if; 	        
			        out1<=n;
		        --end if;
		  end if;
	 end process;
end Behavioral;