ssend.vhd

采用VHDL语言编写的万年历程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ssend is
    Port ( clk,reset : in std_logic;
           add : in std_logic;--频率增加键
           sub : in std_logic;--频率减小键
			  convert:in std_logic_vector(1 downto 0);
		     data0,data1,data2,data3,data4,data5 :out std_logic_vector(3 downto 0 );
			  A: out std_logic_vector(5 downto 0);--分频预置数输出
			  N: out std_logic_vector(9 downto 0));--分频预置数输出
			 
end ssend;

architecture Behavioral of ssend is
 type state is(st0,st1,st11,st2,st22);
 signal s:state ;
 type states is(sst0,sst1,sst2);
 signal sst:states ;
 type statess  is (million,ten_thousand,thousand,hundred,ten,gewei,zhen,wait_s);
signal current :statess;
 signal keyclk,flag:std_logic;
 signal frequence:integer range 0 to 109000;
 signal fm:integer range 0 to 500;
 signal fa:integer range 0 to 50;
 signal FN:integer range 0 to 2;

begin

process(clk,reset)
 variable count2: integer;

		variable clk0: std_logic;
		begin
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 elsif clk'event and clk='1' then
			  count2:=count2+1;
			  if count2=1 then
			  clk0:='1';
			  elsif count2=2 then  ---3200
			    count2:=0;
				 clk0:='0';
		     --end if; 
			 end if;
			end if;
		keyclk<=clk0;
end process;
   process(reset,convert)
	begin
	  if reset='0' then fm<=25;FA<=2;FN<=0;
	  elsif convert="00" then fm<=25;FA<=2;FN<=0;--发射频率增加25KHZ
	  elsif convert="10"then fm<=50;FA<=4;FN<=0;--发射频率减小50KHZ
	  elsif convert="01" then fm<=500;FA<=40;FN<=0;--发射频率减小500KHZ
	  else null;
	  end if;
	end process;

 	process(reset,add,sub,keyclk,fm,fa,fn)--按键进程
	variable fre:integer range 0 to 109000;
	variable AA:integer range -100 to 200;---------------------------------------
   variable NN:integer range 0 to 400;
	begin
	  if reset='0' then
	   s<=st0;fre:=87000; flag<='0';AA:=48;NN:=108;

	  elsif keyclk'event and keyclk='1' then
	  case s is 
	        when st0 => flag<='1';A<=conv_std_logic_vector(AA,6);
			             N<=conv_std_logic_vector(NN,10);
			          if add='0' then s<=st1;flag<='0';
					    elsif sub='0' then
						 s<=st2;flag<='0';
						 end if;
		 	  when st1 =>
			           if add='1' then						   
					       fre:=fre+fm;AA:=AA+fa;NN:=NN+fn;s<=st11;						 
						  end if;
			  when st11 =>
						   if AA>=64 then AA:=AA-64;NN:=NN+1;s<=st0;
							else s<=st0;
						   end if ;
			  when st2 =>
						  if sub='1' then 
                    fre:=fre-fm;AA:=AA-fa;NN:=NN-fn;s<=st22;
						  end if;
			  when st22 =>
			            if (AA>0 or AA=0) then s<=st0;
							else
                     AA:=64+AA;NN:=NN-1;s<=st0;
							end if;
					--	   if AA<=0 then AA:=64+AA;NN:=NN-1;s<=st0;
					--	   else s<=st0;	    	
 					--	   end if ;
		  end case; 
       	  	  

	  end if;
	  frequence<=fre;	
	end process;
 
stata_kk:process(keyclk, frequence)
variable data_ten_th,data_million,data_th,data_hu,data_ten,data_ge :integer range 0 to 10;
variable cnt_zhen,cnt_zhen1 :integer range 0 to 109000;
begin

if reset='0' then 
 cnt_zhen:=frequence;  cnt_zhen1:=frequence;
        data_ten_th:=0;data_million:=0;data_th:=0;data_hu:=0;data_ten:=0;data_ge:=0; current<=zhen;        			
				
              

elsif rising_edge(keyclk) then

case current is

 when zhen => cnt_zhen:=frequence;data_ten_th:=0;cnt_zhen1:=0;
             data_million:=0;data_th:=0;data_hu:=0;data_ten:=0;data_ge:=0;current<=million; 
when million =>if cnt_zhen<100000 then
				    current<=ten_thousand;
					else
					cnt_zhen:=cnt_zhen-100000;
					data_million:=data_million+1;
					end if;
when ten_thousand =>if cnt_zhen<10000 then
				    current<=thousand;
					
					else
					cnt_zhen:=cnt_zhen-10000;
					data_ten_th:=data_ten_th+1;
					end if;
				
when thousand =>
              if cnt_zhen<1000 then
				    current<=hundred;
					
					else
					cnt_zhen:=cnt_zhen-1000;
					data_th:=data_th+1;
					end if;

when hundred =>
              if cnt_zhen<100 then
				    current<=ten;
				
					else
					cnt_zhen:=cnt_zhen-100;
					data_hu:=data_hu+1;
					end if;
when ten =>
              if cnt_zhen<10 then
				    current<=gewei;
					
					else
					cnt_zhen:=cnt_zhen-10;
					data_ten:=data_ten+1;
					end if;
when gewei =>
              if cnt_zhen<1 then
				    current<=wait_s;

					else
					cnt_zhen:=cnt_zhen-1;
					data_ge:=data_ge+1;
					end if;
when wait_s => 
               data0<=conv_std_logic_vector(data_million,4);
               data1<=conv_std_logic_vector(data_ten_th,4);
               data2<=conv_std_logic_vector(data_th,4);
               data3<=conv_std_logic_vector(data_hu,4);
               data4<=conv_std_logic_vector(data_ten,4);
               data5<=conv_std_logic_vector(data_ge,4);
				   current<=zhen;
				
				
				

 when others =>null;
 end case;
 end if;

					 

 end process;

end Behavioral;