data_send.vhd

采用VHDL语言编写的万年历程序

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity data_send is
    Port (sysclk,reset:in std_Logic;
	       data0,data1,data2,data3,data4,data5,data6,data7, data8,data9,data10,data11,data12,data13,data14,data15,data16,data17,data18,data19,data20,data21  : in std_logic_vector(3 downto 0);
	       TXD :out std_logic);
end data_send;

architecture Behavioral of data_send is
signal clock :std_logic;
type state is (st0,st1,st2);
signal current_state : state;
type ram is array(0 to 11) of std_logic_vector(9 downto 0);
signal dataram :ram;
begin

process(sysclk,reset)
 variable count2: integer range 0 to 20000;
		variable clk0: std_logic;
		begin
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 elsif sysclk'event and sysclk='1' then
			  count2:=count2+1;
			  if count2=2560 then
			  clk0:='1';
			  elsif count2=5556 then
			    count2:=0;
				 clk0:='0';
		     --end if; 
			 end if;
			end if;
		clock<=clk0;
end process;
process(clock)
begin
if rising_edge(clock) then
dataram(0)<='1'&data1&data0&'0';dataram(1)<='1'&data3&data2&'0';dataram(2)<='1'&data5&data4&'0';
dataram(3)<='1'&data7&data6&'0';dataram(4)<='1'&data9&data8&'0';dataram(5)<='1'&data11&data10&'0';
dataram(6)<='1'&data13&data12&'0';dataram(7)<='1'&data15&data14&'0';dataram(8)<='1'&data17&data16&'0';
dataram(9)<='1'&data19&data18&'0';dataram(10)<='1'&data21&data20&'0';
dataram(11)<="1111111110";
end if;
end process;


send_data:process(clock,reset)
variable cnt,cnt1,cnt2 :integer range 0 to 20;
variable cnt3 :integer range 0 to 1024;
begin
if reset='0' then
current_state<=st0;
cnt:=0;cnt2:=0;cnt3:=0;
elsif rising_edge(clock) then
case current_state is
when st0=>  TXD<='1';
        
			 current_state<=st1;cnt:=0;cnt1:=0;cnt2:=0;cnt3:=0;
			 
	
when st1=>TXD<=dataram(cnt1)(cnt2);             
           if cnt2<9 then cnt2:=cnt2+1;
			  elsif cnt2=9 then cnt2:=0;
			                    cnt1:=cnt1+1;
			  end if;
			  if cnt1=12 then current_state<=st2;
			  end if;
when st2=>cnt3:=cnt3+1;
          if cnt3=1000 then
			 current_state<=st0;
			 end if;
          
when others=>current_state<=st0;
end case;
end if;
end process send_data;
end Behavioral;