rectangular.vhd

来自「采用VHDL语言写了一个函数发生器的程序。内含有各个模块」· VHDL 代码 · 共 66 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity rectangular is
   Port (clkout,reset :in std_logic;
	       dd:out std_logic_vector(8 downto 0)); 
end rectangular;

architecture Behavioral of rectangular is
signal clk_out :std_logic;
begin


process(clkout,reset)
 variable count2: integer;
		variable clk0: std_logic;
		begin
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 elsif clkout'event and clkout='1' then
			  count2:=count2+1;
			  if count2=180 then
			  clk0:='1';
			  elsif count2=360 then
			    count2:=0;
				 clk0:='0';
		     --end if;
			 end if;
			end if;
		clk_out<=clk0;

end process;


process(clk_out)
variable cnt :integer range 2 downto 0;
begin
if reset='0' then
cnt:=0;
elsif rising_edge(clk_out)  then
 cnt:=cnt+1;
 if cnt=1 then
dd<="111111111";

elsif cnt=2 then
dd<="000000000";
cnt:=0;
end if;
end if;

end process;
	

 
end Behavioral;