pulse.vhd

来自「采用VHDL语言设计了一个打铃系统。该系统已经调试」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pulse is
    Port ( clock,en:in std_logic;
	             clk:out std_logic
	 );
end pulse;

architecture Behavioral of pulse is

begin
 counter: process(clock,en)
	   variable count2: integer;
		variable clk0: std_logic;
		begin
		   if  en='0' then
			           count2:=0;
			             clk0:='0';
		   elsif clock'event and clock='1' then
			                     count2:=count2+1;
			     if count2=16000000 then
			             clk0:='1';
			     elsif count2=32000000 then
			                        count2:=0;
				                     clk0:='0';
		               --end if;
			     end if;
		   end if;
		clk<=clk0;
	 end process counter;

end Behavioral;