ring.vhd

采用VHDL语言设计了一个打铃系统。该系统已经调试

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ring is
    Port (ringing2:out std_logic;
			 clock2:in std_logic;
			 dclk2:in integer;
			 reset2:in std_logic
			 );
end ring;

architecture Behavioral of ring is
    signal sign2:integer;
begin
   process(clock2,reset2,sign2,dclk2)
   variable bdclk:integer;
     begin
	  if reset2='0' then
	     bdclk:=dclk2;
	  elsif clock2'event and clock2='1' then
		           bdclk:=bdclk+1;
			if bdclk=86400 then
				     bdclk:=0;
		   end if;
	  end if;
		 sign2<=bdclk;
end process;

process(clock2,sign2)
    begin
	  if clock2'event and clock2='1' then
     case sign2 is
	      when 28800 to 28810=>ringing2<='1';--1
			when 28811 to 31500=>ringing2<='0';
			when 31501 to 31510=>ringing2<='1';
			when 31511 to 32100=>ringing2<='0';
			when 32101 to 32110=>ringing2<='1';--2
			when 32111 to 34800=>ringing2<='0';
			when 34801 to 34810=>ringing2<='1';
			when 34811 to 36000=>ringing2<='0';
			when 36001 to 36010=>ringing2<='1';--3
			when 36011 to 38700=>ringing2<='0';
			when 38701 to 38710=>ringing2<='1';
			when 38711 to 39300=>ringing2<='0';
			when 39301 to 39310=>ringing2<='1';--4
			when 39311 to 42000=>ringing2<='0';
			when 42001 to 42010=>ringing2<='1';
			when 42011 to 52200=>ringing2<='0';
			when 52201 to 52210=>ringing2<='1';--5
			when 52211 to 54900=>ringing2<='0';
			when 54901 to 54910=>ringing2<='1';
			when 54911 to 55500=>ringing2<='0';
			when 55501 to 55510=>ringing2<='1';--6
			when 55511 to 58200=>ringing2<='0';
			when 58201 to 58210=>ringing2<='1';
			when others=>ringing2<='0';
			end case;
	  end if;
end process;

end Behavioral;