📄 count_100.rpt
字号:
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 4/ 96( 4%) 3/ 48( 6%) 4/ 48( 8%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock_second\count_100.rpt
count_100
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
DFF 5 |COUNT_10:9|:3
Device-Specific Information: c:\clock_second\count_100.rpt
count_100
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 clr
Device-Specific Information: c:\clock_second\count_100.rpt
count_100
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC1_B16, type is buried.
-- synthesized logic cell
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL(!clr);
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC5_B22;
-- Node name is 'gewei0'
-- Equation name is 'gewei0', type is output
gewei0 = _LC4_B1;
-- Node name is 'gewei1'
-- Equation name is 'gewei1', type is output
gewei1 = _LC6_B1;
-- Node name is 'gewei2'
-- Equation name is 'gewei2', type is output
gewei2 = _LC1_B1;
-- Node name is 'gewei3'
-- Equation name is 'gewei3', type is output
gewei3 = _LC8_B1;
-- Node name is 'shiwei0'
-- Equation name is 'shiwei0', type is output
shiwei0 = _LC1_B22;
-- Node name is 'shiwei1'
-- Equation name is 'shiwei1', type is output
shiwei1 = _LC3_B22;
-- Node name is 'shiwei2'
-- Equation name is 'shiwei2', type is output
shiwei2 = _LC2_B22;
-- Node name is 'shiwei3'
-- Equation name is 'shiwei3', type is output
shiwei3 = _LC6_B22;
-- Node name is '|COUNT_10:9|:12' = '|COUNT_10:9|coun_100'
-- Equation name is '_LC4_B1', type is buried
_LC4_B1 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = _LC4_B1 & !_LC5_B1 & _LC8_B1
# _LC2_B1 & !_LC4_B1 & !_LC5_B1;
-- Node name is '|COUNT_10:9|:11' = '|COUNT_10:9|coun_101'
-- Equation name is '_LC6_B1', type is buried
_LC6_B1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC4_B1 & _LC6_B1
# _LC4_B1 & !_LC6_B1 & !_LC8_B1
# _LC6_B1 & _LC8_B1;
-- Node name is '|COUNT_10:9|:10' = '|COUNT_10:9|coun_102'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = _LC1_B1 & !_LC6_B1
# _LC1_B1 & !_LC4_B1
# !_LC1_B1 & _LC4_B1 & _LC6_B1 & !_LC8_B1
# _LC1_B1 & _LC8_B1;
-- Node name is '|COUNT_10:9|:9' = '|COUNT_10:9|coun_103'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = !_LC4_B1 & _LC8_B1
# _LC1_B1 & _LC4_B1 & _LC6_B1
# _LC1_B1 & _LC8_B1
# _LC6_B1 & _LC8_B1;
-- Node name is '|COUNT_10:9|:3'
-- Equation name is '_LC4_B22', type is buried
_LC4_B22 = DFFE( _LC5_B1, GLOBAL( clk), VCC, VCC, !_LC1_B16);
-- Node name is '|COUNT_10:9|:53'
-- Equation name is '_LC5_B1', type is buried
!_LC5_B1 = _LC5_B1~NOT;
_LC5_B1~NOT = LCELL( _EQ005);
_EQ005 = !_LC8_B1
# !_LC4_B1
# _LC1_B1
# _LC6_B1;
-- Node name is '|COUNT_10:9|:62'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = LCELL( _EQ006);
_EQ006 = !_LC8_B1
# !_LC1_B1 & !_LC4_B1 & !_LC6_B1;
-- Node name is '|COUNT_10:10|:12' = '|COUNT_10:10|coun_100'
-- Equation name is '_LC1_B22', type is buried
_LC1_B22 = DFFE( _EQ007, _LC4_B22, GLOBAL(!clr), VCC, VCC);
_EQ007 = _LC1_B22 & _LC6_B22 & !_LC7_B22
# !_LC1_B22 & !_LC7_B22 & _LC8_B22;
-- Node name is '|COUNT_10:10|:11' = '|COUNT_10:10|coun_101'
-- Equation name is '_LC3_B22', type is buried
_LC3_B22 = DFFE( _EQ008, _LC4_B22, GLOBAL(!clr), VCC, VCC);
_EQ008 = !_LC1_B22 & _LC3_B22
# _LC1_B22 & !_LC3_B22 & !_LC6_B22
# _LC3_B22 & _LC6_B22;
-- Node name is '|COUNT_10:10|:10' = '|COUNT_10:10|coun_102'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = DFFE( _EQ009, _LC4_B22, GLOBAL(!clr), VCC, VCC);
_EQ009 = _LC2_B22 & !_LC3_B22
# !_LC1_B22 & _LC2_B22
# _LC1_B22 & !_LC2_B22 & _LC3_B22 & !_LC6_B22
# _LC2_B22 & _LC6_B22;
-- Node name is '|COUNT_10:10|:9' = '|COUNT_10:10|coun_103'
-- Equation name is '_LC6_B22', type is buried
_LC6_B22 = DFFE( _EQ010, _LC4_B22, GLOBAL(!clr), VCC, VCC);
_EQ010 = _LC1_B22 & _LC2_B22 & _LC3_B22
# _LC2_B22 & _LC6_B22
# _LC3_B22 & _LC6_B22
# !_LC1_B22 & _LC6_B22;
-- Node name is '|COUNT_10:10|:3'
-- Equation name is '_LC5_B22', type is buried
_LC5_B22 = DFFE( _LC7_B22, _LC4_B22, VCC, VCC, !_LC1_B16);
-- Node name is '|COUNT_10:10|:53'
-- Equation name is '_LC7_B22', type is buried
!_LC7_B22 = _LC7_B22~NOT;
_LC7_B22~NOT = LCELL( _EQ011);
_EQ011 = _LC2_B22
# _LC3_B22
# !_LC6_B22
# !_LC1_B22;
-- Node name is '|COUNT_10:10|:62'
-- Equation name is '_LC8_B22', type is buried
_LC8_B22 = LCELL( _EQ012);
_EQ012 = !_LC6_B22
# !_LC1_B22 & !_LC2_B22 & !_LC3_B22;
Project Information c:\clock_second\count_100.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,487K
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