📄 mux_24_4.rpt
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09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock_second\mux_24_4.rpt
mux_24_4
** EQUATIONS **
count0 : INPUT;
count1 : INPUT;
count2 : INPUT;
hao_ge0 : INPUT;
hao_ge1 : INPUT;
hao_ge2 : INPUT;
hao_ge3 : INPUT;
hao_shi0 : INPUT;
hao_shi1 : INPUT;
hao_shi2 : INPUT;
hao_shi3 : INPUT;
min_ge0 : INPUT;
min_ge1 : INPUT;
min_ge2 : INPUT;
min_ge3 : INPUT;
min_shi0 : INPUT;
min_shi1 : INPUT;
min_shi2 : INPUT;
min_shi3 : INPUT;
sec_ge0 : INPUT;
sec_ge1 : INPUT;
sec_ge2 : INPUT;
sec_ge3 : INPUT;
sec_shi0 : INPUT;
sec_shi1 : INPUT;
sec_shi2 : INPUT;
sec_shi3 : INPUT;
-- Node name is 'bcd0'
-- Equation name is 'bcd0', type is output
bcd0 = _LC5_B5;
-- Node name is 'bcd1'
-- Equation name is 'bcd1', type is output
bcd1 = _LC7_B4;
-- Node name is 'bcd2'
-- Equation name is 'bcd2', type is output
bcd2 = _LC8_B12;
-- Node name is 'bcd3'
-- Equation name is 'bcd3', type is output
bcd3 = _LC4_B9;
-- Node name is ':38'
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ001);
_EQ001 = !count0 & !count1 & !count2;
-- Node name is ':42'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = LCELL( _EQ002);
_EQ002 = count0 & !count1 & !count2;
-- Node name is ':46'
-- Equation name is '_LC2_B5', type is buried
_LC2_B5 = LCELL( _EQ003);
_EQ003 = !count0 & count1 & !count2;
-- Node name is ':50'
-- Equation name is '_LC8_B4', type is buried
!_LC8_B4 = _LC8_B4~NOT;
_LC8_B4~NOT = LCELL( _EQ004);
_EQ004 = count2
# !count1
# !count0;
-- Node name is ':78'
-- Equation name is '_LC6_B2', type is buried
_LC6_B2 = LCELL( _EQ005);
_EQ005 = !count0 & !count1 & count2 & min_ge3;
-- Node name is ':79'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = LCELL( _EQ006);
_EQ006 = count1
# !count2
# count0 & min_shi3;
-- Node name is ':83'
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ007);
_EQ007 = _LC8_B4 & sec_shi3
# _LC5_B2 & !_LC8_B4
# _LC6_B2 & !_LC8_B4;
-- Node name is ':89'
-- Equation name is '_LC1_B9', type is buried
_LC1_B9 = LCELL( _EQ008);
_EQ008 = _LC1_B2 & !_LC2_B5
# _LC2_B5 & sec_ge3;
-- Node name is ':95'
-- Equation name is '_LC2_B9', type is buried
_LC2_B9 = LCELL( _EQ009);
_EQ009 = !_LC1_B5 & _LC1_B9
# hao_shi3 & _LC1_B5;
-- Node name is ':101'
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = LCELL( _EQ010);
_EQ010 = !_LC1_B4 & _LC2_B9
# hao_ge3 & _LC1_B4;
-- Node name is ':111'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = LCELL( _EQ011);
_EQ011 = !count0 & !count1 & count2 & min_ge2;
-- Node name is ':112'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = LCELL( _EQ012);
_EQ012 = count1
# !count2
# count0 & min_shi2;
-- Node name is ':113'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = LCELL( _EQ013);
_EQ013 = _LC8_B4 & sec_shi2
# _LC3_B2 & !_LC8_B4
# _LC4_B2 & !_LC8_B4;
-- Node name is ':116'
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = LCELL( _EQ014);
_EQ014 = _LC2_B2 & !_LC2_B5
# _LC2_B5 & sec_ge2;
-- Node name is ':119'
-- Equation name is '_LC2_B12', type is buried
_LC2_B12 = LCELL( _EQ015);
_EQ015 = !_LC1_B5 & _LC1_B12
# hao_shi2 & _LC1_B5;
-- Node name is ':122'
-- Equation name is '_LC8_B12', type is buried
_LC8_B12 = LCELL( _EQ016);
_EQ016 = !_LC1_B4 & _LC2_B12
# hao_ge2 & _LC1_B4;
-- Node name is ':132'
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ017);
_EQ017 = !count0 & !count1 & count2 & min_ge1;
-- Node name is ':133'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = LCELL( _EQ018);
_EQ018 = count1
# !count2
# count0 & min_shi1;
-- Node name is ':134'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = LCELL( _EQ019);
_EQ019 = _LC8_B4 & sec_shi1
# _LC2_B4 & !_LC8_B4
# _LC3_B4 & !_LC8_B4;
-- Node name is ':137'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = LCELL( _EQ020);
_EQ020 = !_LC2_B5 & _LC4_B4
# _LC2_B5 & sec_ge1;
-- Node name is ':140'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ021);
_EQ021 = !_LC1_B5 & _LC5_B4
# hao_shi1 & _LC1_B5;
-- Node name is ':143'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ022);
_EQ022 = !_LC1_B4 & _LC6_B4
# hao_ge1 & _LC1_B4;
-- Node name is ':153'
-- Equation name is '_LC4_B5', type is buried
_LC4_B5 = LCELL( _EQ023);
_EQ023 = !count0 & !count1 & count2 & min_ge0;
-- Node name is ':154'
-- Equation name is '_LC3_B5', type is buried
_LC3_B5 = LCELL( _EQ024);
_EQ024 = count1
# !count2
# count0 & min_shi0;
-- Node name is ':155'
-- Equation name is '_LC6_B5', type is buried
_LC6_B5 = LCELL( _EQ025);
_EQ025 = _LC8_B4 & sec_shi0
# _LC3_B5 & !_LC8_B4
# _LC4_B5 & !_LC8_B4;
-- Node name is ':158'
-- Equation name is '_LC7_B5', type is buried
_LC7_B5 = LCELL( _EQ026);
_EQ026 = !_LC2_B5 & _LC6_B5
# _LC2_B5 & sec_ge0;
-- Node name is ':161'
-- Equation name is '_LC8_B5', type is buried
_LC8_B5 = LCELL( _EQ027);
_EQ027 = !_LC1_B5 & _LC7_B5
# hao_shi0 & _LC1_B5;
-- Node name is ':164'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = LCELL( _EQ028);
_EQ028 = !_LC1_B4 & _LC8_B5
# hao_ge0 & _LC1_B4;
Project Information c:\clock_second\mux_24_4.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,154K
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