📄 zt.rpt
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# !_LC5_B13 & _LC7_B13 & _LC8_B13;
-- Node name is '|DISP_COUNT:6|:25'
-- Equation name is '_LC5_B13', type is buried
!_LC5_B13 = _LC5_B13~NOT;
_LC5_B13~NOT = LCELL( _EQ043);
_EQ043 = _LC8_B13
# !_LC3_B13
# !_LC7_B13;
-- Node name is '|MUX_24_4:1|:77'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = LCELL( _EQ044);
_EQ044 = !_LC5_B13 & !_LC6_B13
# !_LC6_B13 & _LC7_B15
# _LC3_B14 & _LC6_B13;
-- Node name is '|MUX_24_4:1|:83'
-- Equation name is '_LC2_B22', type is buried
_LC2_B22 = LCELL( _EQ045);
_EQ045 = !_LC1_B13 & _LC1_B14
# _LC1_B13 & _LC6_B22;
-- Node name is '|MUX_24_4:1|:89'
-- Equation name is '_LC4_B23', type is buried
_LC4_B23 = LCELL( _EQ046);
_EQ046 = _LC2_B22 & !_LC7_B23
# _LC3_B20 & _LC7_B23;
-- Node name is '|MUX_24_4:1|:95'
-- Equation name is '_LC2_B23', type is buried
_LC2_B23 = LCELL( _EQ047);
_EQ047 = !_LC2_B13 & _LC4_B23
# _LC2_B13 & _LC4_B24;
-- Node name is '|MUX_24_4:1|:101'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = LCELL( _EQ048);
_EQ048 = _LC2_B23 & !_LC4_B13
# _LC4_B13 & _LC5_B17;
-- Node name is '|MUX_24_4:1|:110'
-- Equation name is '_LC5_B21', type is buried
!_LC5_B21 = _LC5_B21~NOT;
_LC5_B21~NOT = LCELL( _EQ049);
_EQ049 = !_LC3_B15 & _LC5_B13 & !_LC6_B13
# !_LC3_B15 & !_LC4_B14 & _LC5_B13
# !_LC4_B14 & _LC6_B13;
-- Node name is '|MUX_24_4:1|:113'
-- Equation name is '_LC6_B21', type is buried
!_LC6_B21 = _LC6_B21~NOT;
_LC6_B21~NOT = LCELL( _EQ050);
_EQ050 = !_LC1_B13 & !_LC5_B21
# !_LC4_B22 & !_LC5_B21
# _LC1_B13 & !_LC4_B22;
-- Node name is '|MUX_24_4:1|:116'
-- Equation name is '_LC7_B21', type is buried
!_LC7_B21 = _LC7_B21~NOT;
_LC7_B21~NOT = LCELL( _EQ051);
_EQ051 = !_LC6_B21 & !_LC7_B23
# !_LC2_B20 & !_LC6_B21
# !_LC2_B20 & _LC7_B23;
-- Node name is '|MUX_24_4:1|:119'
-- Equation name is '_LC8_B21', type is buried
!_LC8_B21 = _LC8_B21~NOT;
_LC8_B21~NOT = LCELL( _EQ052);
_EQ052 = !_LC2_B13 & !_LC7_B21
# !_LC2_B24 & !_LC7_B21
# _LC2_B13 & !_LC2_B24;
-- Node name is '|MUX_24_4:1|:122'
-- Equation name is '_LC3_B21', type is buried
!_LC3_B21 = _LC3_B21~NOT;
_LC3_B21~NOT = LCELL( _EQ053);
_EQ053 = !_LC4_B13 & !_LC8_B21
# !_LC6_B17 & !_LC8_B21
# _LC4_B13 & !_LC6_B17;
-- Node name is '|MUX_24_4:1|:131'
-- Equation name is '_LC4_B21', type is buried
!_LC4_B21 = _LC4_B21~NOT;
_LC4_B21~NOT = LCELL( _EQ054);
_EQ054 = !_LC4_B15 & _LC5_B13 & !_LC6_B13
# !_LC2_B14 & !_LC4_B15 & _LC5_B13
# !_LC2_B14 & _LC6_B13;
-- Node name is '|MUX_24_4:1|:134'
-- Equation name is '_LC1_B21', type is buried
!_LC1_B21 = _LC1_B21~NOT;
_LC1_B21~NOT = LCELL( _EQ055);
_EQ055 = !_LC1_B13 & !_LC4_B21
# !_LC4_B21 & !_LC5_B22
# _LC1_B13 & !_LC5_B22;
-- Node name is '|MUX_24_4:1|:137'
-- Equation name is '_LC3_B23', type is buried
!_LC3_B23 = _LC3_B23~NOT;
_LC3_B23~NOT = LCELL( _EQ056);
_EQ056 = !_LC1_B21 & !_LC7_B23
# !_LC1_B21 & !_LC5_B20
# !_LC5_B20 & _LC7_B23;
-- Node name is '|MUX_24_4:1|:140'
-- Equation name is '_LC1_B23', type is buried
!_LC1_B23 = _LC1_B23~NOT;
_LC1_B23~NOT = LCELL( _EQ057);
_EQ057 = !_LC2_B13 & !_LC3_B23
# !_LC3_B23 & !_LC5_B24
# _LC2_B13 & !_LC5_B24;
-- Node name is '|MUX_24_4:1|:143'
-- Equation name is '_LC4_B16', type is buried
!_LC4_B16 = _LC4_B16~NOT;
_LC4_B16~NOT = LCELL( _EQ058);
_EQ058 = !_LC1_B23 & !_LC4_B13
# !_LC1_B23 & !_LC4_B17
# _LC4_B13 & !_LC4_B17;
-- Node name is '|MUX_24_4:1|:152'
-- Equation name is '_LC7_B14', type is buried
!_LC7_B14 = _LC7_B14~NOT;
_LC7_B14~NOT = LCELL( _EQ059);
_EQ059 = !_LC1_B15 & _LC5_B13 & !_LC6_B13
# !_LC1_B15 & _LC5_B13 & !_LC6_B14
# _LC6_B13 & !_LC6_B14;
-- Node name is '|MUX_24_4:1|:155'
-- Equation name is '_LC2_B21', type is buried
!_LC2_B21 = _LC2_B21~NOT;
_LC2_B21~NOT = LCELL( _EQ060);
_EQ060 = !_LC1_B13 & !_LC7_B14
# !_LC3_B22 & !_LC7_B14
# _LC1_B13 & !_LC3_B22;
-- Node name is '|MUX_24_4:1|:158'
-- Equation name is '_LC8_B20', type is buried
!_LC8_B20 = _LC8_B20~NOT;
_LC8_B20~NOT = LCELL( _EQ061);
_EQ061 = !_LC2_B21 & !_LC7_B23
# !_LC2_B21 & !_LC7_B20
# !_LC7_B20 & _LC7_B23;
-- Node name is '|MUX_24_4:1|:161'
-- Equation name is '_LC4_B20', type is buried
!_LC4_B20 = _LC4_B20~NOT;
_LC4_B20~NOT = LCELL( _EQ062);
_EQ062 = !_LC2_B13 & !_LC8_B20
# !_LC3_B24 & !_LC8_B20
# _LC2_B13 & !_LC3_B24;
-- Node name is '|MUX_24_4:1|:164'
-- Equation name is '_LC2_B17', type is buried
!_LC2_B17 = _LC2_B17~NOT;
_LC2_B17~NOT = LCELL( _EQ063);
_EQ063 = !_LC4_B13 & !_LC4_B20
# !_LC4_B20 & !_LC8_B17
# _LC4_B13 & !_LC8_B17;
-- Node name is '|SEG_SELECT:17|:162'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ064);
_EQ064 = _LC3_B13 & !_LC7_B13 & !_LC8_B13;
-- Node name is '|SEG_SELECT:17|:172'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ065);
_EQ065 = !_LC3_B13 & _LC7_B13 & _LC8_B13;
-- Node name is '|SEG_SELECT:17|:182'
-- Equation name is '_LC7_B23', type is buried
_LC7_B23 = LCELL( _EQ066);
_EQ066 = !_LC3_B13 & !_LC7_B13 & _LC8_B13;
-- Node name is '|SEG_SELECT:17|:192'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ067);
_EQ067 = !_LC3_B13 & _LC7_B13 & !_LC8_B13;
-- Node name is '|SEG_SELECT:17|:202'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ068);
_EQ068 = !_LC3_B13 & !_LC7_B13 & !_LC8_B13;
-- Node name is '|7400:5|:4' = '|7400:5|1'
-- Equation name is '_LC7_B18', type is buried
_LC7_B18 = LCELL( _EQ069);
_EQ069 = stop
# !clk;
-- Node name is ':10'
-- Equation name is '_LC8_B15', type is buried
!_LC8_B15 = _LC8_B15~NOT;
_LC8_B15~NOT = LCELL( _EQ070);
_EQ070 = clear & !_LC6_B15;
Project Information d:\vhdl\shiyan3_24\zt.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:06
Database Builder 00:00:00
Logic Synthesizer 00:00:02
Partitioner 00:00:03
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:16
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,295K
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