📄 zt.rpt
字号:
66 - - B -- OUTPUT 0 1 0 0 L5
49 - - - 16 OUTPUT 0 1 0 0 L6
83 - - - 13 OUTPUT 0 1 0 0 seg0
22 - - B -- OUTPUT 0 1 0 0 seg1
64 - - B -- OUTPUT 0 1 0 0 seg2
67 - - B -- OUTPUT 0 1 0 0 seg3
24 - - B -- OUTPUT 0 1 0 0 seg4
65 - - B -- OUTPUT 0 1 0 0 seg5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\vhdl\shiyan3_24\zt.rpt
zt
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:375
- 2 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:408
- 3 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:441
- 8 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:474
- 5 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:507
- 1 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:540
- 7 - B 16 OR2 0 4 1 0 |BCD_DECODER:2|:575
- 6 - B 15 DFFE 0 3 0 1 |count_60:8|COUNT_6:2|:3
- 7 - B 15 DFFE 0 2 0 5 |count_60:8|COUNT_6:2|coun_63 (|count_60:8|COUNT_6:2|:9)
- 3 - B 15 DFFE 0 5 0 4 |count_60:8|COUNT_6:2|coun_62 (|count_60:8|COUNT_6:2|:10)
- 4 - B 15 DFFE 0 5 0 4 |count_60:8|COUNT_6:2|coun_61 (|count_60:8|COUNT_6:2|:11)
- 1 - B 15 DFFE 0 5 0 4 |count_60:8|COUNT_6:2|coun_60 (|count_60:8|COUNT_6:2|:12)
- 5 - B 15 AND2 0 4 0 1 |count_60:8|COUNT_6:2|:53
- 2 - B 15 DFFE 0 3 0 5 |count_60:8|COUNT_10:1|:3
- 3 - B 14 DFFE 0 5 0 6 |count_60:8|COUNT_10:1|coun_103 (|count_60:8|COUNT_10:1|:9)
- 4 - B 14 DFFE 0 5 0 4 |count_60:8|COUNT_10:1|coun_102 (|count_60:8|COUNT_10:1|:10)
- 2 - B 14 DFFE 0 4 0 5 |count_60:8|COUNT_10:1|coun_101 (|count_60:8|COUNT_10:1|:11)
- 6 - B 14 DFFE 0 5 0 6 |count_60:8|COUNT_10:1|coun_100 (|count_60:8|COUNT_10:1|:12)
- 8 - B 14 OR2 ! 0 4 0 2 |count_60:8|COUNT_10:1|:53
- 5 - B 14 OR2 0 4 0 1 |count_60:8|COUNT_10:1|:62
- 1 - B 22 DFFE 0 3 0 5 |count_60:9|COUNT_6:2|:3
- 6 - B 22 DFFE 0 2 0 5 |count_60:9|COUNT_6:2|coun_63 (|count_60:9|COUNT_6:2|:9)
- 4 - B 22 DFFE 0 5 0 4 |count_60:9|COUNT_6:2|coun_62 (|count_60:9|COUNT_6:2|:10)
- 5 - B 22 DFFE 0 5 0 4 |count_60:9|COUNT_6:2|coun_61 (|count_60:9|COUNT_6:2|:11)
- 3 - B 22 DFFE 0 5 0 4 |count_60:9|COUNT_6:2|coun_60 (|count_60:9|COUNT_6:2|:12)
- 8 - B 22 AND2 0 4 0 1 |count_60:9|COUNT_6:2|:53
- 7 - B 22 DFFE 0 3 0 5 |count_60:9|COUNT_10:1|:3
- 3 - B 20 DFFE 0 5 0 6 |count_60:9|COUNT_10:1|coun_103 (|count_60:9|COUNT_10:1|:9)
- 2 - B 20 DFFE 0 5 0 4 |count_60:9|COUNT_10:1|coun_102 (|count_60:9|COUNT_10:1|:10)
- 5 - B 20 DFFE 0 4 0 5 |count_60:9|COUNT_10:1|coun_101 (|count_60:9|COUNT_10:1|:11)
- 7 - B 20 DFFE 0 5 0 6 |count_60:9|COUNT_10:1|coun_100 (|count_60:9|COUNT_10:1|:12)
- 1 - B 20 OR2 ! 0 4 0 2 |count_60:9|COUNT_10:1|:53
- 6 - B 20 OR2 0 4 0 1 |count_60:9|COUNT_10:1|:62
- 7 - B 24 DFFE 0 3 0 5 |count_100:7|COUNT_10:9|:3
- 5 - B 17 DFFE 0 5 0 6 |count_100:7|COUNT_10:9|coun_103 (|count_100:7|COUNT_10:9|:9)
- 6 - B 17 DFFE 0 5 0 4 |count_100:7|COUNT_10:9|coun_102 (|count_100:7|COUNT_10:9|:10)
- 4 - B 17 DFFE 0 4 0 5 |count_100:7|COUNT_10:9|coun_101 (|count_100:7|COUNT_10:9|:11)
- 8 - B 17 DFFE 0 5 0 6 |count_100:7|COUNT_10:9|coun_100 (|count_100:7|COUNT_10:9|:12)
- 1 - B 17 AND2 0 4 0 2 |count_100:7|COUNT_10:9|:53
- 7 - B 17 OR2 0 4 0 1 |count_100:7|COUNT_10:9|:62
- 1 - B 24 DFFE 0 3 0 5 |count_100:7|COUNT_10:10|:3
- 4 - B 24 DFFE 0 5 0 6 |count_100:7|COUNT_10:10|coun_103 (|count_100:7|COUNT_10:10|:9)
- 2 - B 24 DFFE 0 5 0 4 |count_100:7|COUNT_10:10|coun_102 (|count_100:7|COUNT_10:10|:10)
- 5 - B 24 DFFE 0 4 0 5 |count_100:7|COUNT_10:10|coun_101 (|count_100:7|COUNT_10:10|:11)
- 3 - B 24 DFFE 0 5 0 6 |count_100:7|COUNT_10:10|coun_100 (|count_100:7|COUNT_10:10|:12)
- 6 - B 24 AND2 0 4 0 2 |count_100:7|COUNT_10:10|:53
- 8 - B 24 OR2 0 4 0 1 |count_100:7|COUNT_10:10|:62
- 3 - B 13 DFFE + 0 3 0 8 |DISP_COUNT:6|coun_62 (|DISP_COUNT:6|:5)
- 8 - B 13 DFFE + 0 3 0 8 |DISP_COUNT:6|coun_61 (|DISP_COUNT:6|:6)
- 7 - B 13 DFFE + 0 3 0 8 |DISP_COUNT:6|coun_60 (|DISP_COUNT:6|:7)
- 5 - B 13 OR2 ! 0 3 1 7 |DISP_COUNT:6|:25
- 1 - B 14 OR2 0 4 0 1 |MUX_24_4:1|:77
- 2 - B 22 OR2 0 3 0 1 |MUX_24_4:1|:83
- 4 - B 23 OR2 0 3 0 1 |MUX_24_4:1|:89
- 2 - B 23 OR2 0 3 0 1 |MUX_24_4:1|:95
- 3 - B 17 OR2 0 3 0 7 |MUX_24_4:1|:101
- 5 - B 21 OR2 ! 0 4 0 1 |MUX_24_4:1|:110
- 6 - B 21 OR2 ! 0 3 0 1 |MUX_24_4:1|:113
- 7 - B 21 OR2 ! 0 3 0 1 |MUX_24_4:1|:116
- 8 - B 21 OR2 ! 0 3 0 1 |MUX_24_4:1|:119
- 3 - B 21 OR2 ! 0 3 0 7 |MUX_24_4:1|:122
- 4 - B 21 OR2 ! 0 4 0 1 |MUX_24_4:1|:131
- 1 - B 21 OR2 ! 0 3 0 1 |MUX_24_4:1|:134
- 3 - B 23 OR2 ! 0 3 0 1 |MUX_24_4:1|:137
- 1 - B 23 OR2 ! 0 3 0 1 |MUX_24_4:1|:140
- 4 - B 16 OR2 ! 0 3 0 7 |MUX_24_4:1|:143
- 7 - B 14 OR2 ! 0 4 0 1 |MUX_24_4:1|:152
- 2 - B 21 OR2 ! 0 3 0 1 |MUX_24_4:1|:155
- 8 - B 20 OR2 ! 0 3 0 1 |MUX_24_4:1|:158
- 4 - B 20 OR2 ! 0 3 0 1 |MUX_24_4:1|:161
- 2 - B 17 OR2 ! 0 3 0 7 |MUX_24_4:1|:164
- 6 - B 13 AND2 0 3 1 4 |SEG_SELECT:17|:162
- 1 - B 13 AND2 0 3 1 4 |SEG_SELECT:17|:172
- 7 - B 23 AND2 0 3 1 4 |SEG_SELECT:17|:182
- 2 - B 13 AND2 0 3 1 4 |SEG_SELECT:17|:192
- 4 - B 13 AND2 0 3 1 4 |SEG_SELECT:17|:202
- 8 - B 15 AND2 ! 1 1 0 30 :10
- 7 - B 18 OR2 2 0 0 5 |7400:5|1 (|7400:5|:4)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\vhdl\shiyan3_24\zt.rpt
zt
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 2/ 48( 4%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
B: 15/ 96( 15%) 0/ 48( 0%) 36/ 48( 75%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\vhdl\shiyan3_24\zt.rpt
zt
** CLOCK SIGNALS **
Type Fan-out Name
DFF 5 |count_60:8|COUNT_10:1|:3
DFF 5 |count_60:9|COUNT_6:2|:3
DFF 5 |count_60:9|COUNT_10:1|:3
DFF 5 |count_100:7|COUNT_10:9|:3
DFF 5 |count_100:7|COUNT_10:10|:3
LCELL 5 |7400:5|1
INPUT 3 fast_clk
Device-Specific Information: d:\vhdl\shiyan3_24\zt.rpt
zt
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 30 :10
Device-Specific Information: d:\vhdl\shiyan3_24\zt.rpt
zt
** EQUATIONS **
clear : INPUT;
clk : INPUT;
fast_clk : INPUT;
stop : INPUT;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = _LC7_B16;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC1_B16;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC5_B16;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC8_B16;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC3_B16;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC2_B16;
-- Node name is 'L6'
-- Equation name is 'L6', type is output
L6 = _LC6_B16;
-- Node name is 'seg0'
-- Equation name is 'seg0', type is output
seg0 = _LC4_B13;
-- Node name is 'seg1'
-- Equation name is 'seg1', type is output
seg1 = _LC2_B13;
-- Node name is 'seg2'
-- Equation name is 'seg2', type is output
seg2 = _LC7_B23;
-- Node name is 'seg3'
-- Equation name is 'seg3', type is output
seg3 = _LC1_B13;
-- Node name is 'seg4'
-- Equation name is 'seg4', type is output
seg4 = _LC6_B13;
-- Node name is 'seg5'
-- Equation name is 'seg5', type is output
seg5 = _LC5_B13;
-- Node name is '|BCD_DECODER:2|:375'
-- Equation name is '_LC6_B16', type is buried
_LC6_B16 = LCELL( _EQ001);
_EQ001 = _LC2_B17 & !_LC3_B17 & _LC3_B21
# !_LC3_B17 & _LC4_B16
# _LC3_B17 & !_LC3_B21 & !_LC4_B16
# !_LC2_B17 & !_LC3_B17 & !_LC3_B21;
-- Node name is '|BCD_DECODER:2|:408'
-- Equation name is '_LC2_B16', type is buried
_LC2_B16 = LCELL( _EQ002);
_EQ002 = !_LC3_B21 & !_LC4_B16
# _LC2_B17 & !_LC3_B17 & _LC4_B16
# !_LC2_B17 & !_LC3_B17 & !_LC4_B16
# !_LC3_B17 & !_LC3_B21;
-- Node name is '|BCD_DECODER:2|:441'
-- Equation name is '_LC3_B16', type is buried
_LC3_B16 = LCELL( _EQ003);
_EQ003 = _LC2_B17 & !_LC3_B17
# !_LC3_B17 & !_LC4_B16
# !_LC3_B21 & !_LC4_B16
# !_LC3_B17 & _LC3_B21;
-- Node name is '|BCD_DECODER:2|:474'
-- Equation name is '_LC8_B16', type is buried
_LC8_B16 = LCELL( _EQ004);
_EQ004 = !_LC2_B17 & !_LC3_B17 & !_LC3_B21
# !_LC3_B17 & !_LC3_B21 & _LC4_B16
# _LC2_B17 & !_LC3_B17 & _LC3_B21 & !_LC4_B16
# !_LC2_B17 & !_LC3_B17 & _LC4_B16
# !_LC2_B17 & !_LC3_B21 & !_LC4_B16
# _LC3_B17 & !_LC3_B21 & !_LC4_B16;
-- Node name is '|BCD_DECODER:2|:507'
-- Equation name is '_LC5_B16', type is buried
_LC5_B16 = LCELL( _EQ005);
_EQ005 = !_LC2_B17 & !_LC3_B17 & !_LC3_B21
# !_LC2_B17 & !_LC3_B21 & !_LC4_B16
# !_LC2_B17 & !_LC3_B17 & _LC4_B16;
-- Node name is '|BCD_DECODER:2|:540'
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