📄 bcd_decoder.rpt
字号:
- 3 - A 05 OR2 4 0 1 0 :507
- 1 - A 04 OR2 4 0 1 0 :540
- 4 - A 03 OR2 4 0 1 0 :575
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\clock_second\bcd_decoder.rpt
bcd_decoder
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock_second\bcd_decoder.rpt
bcd_decoder
** EQUATIONS **
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
-- Node name is 'y0'
-- Equation name is 'y0', type is output
y0 = _LC4_A3;
-- Node name is 'y1'
-- Equation name is 'y1', type is output
y1 = _LC1_A4;
-- Node name is 'y2'
-- Equation name is 'y2', type is output
y2 = _LC3_A5;
-- Node name is 'y3'
-- Equation name is 'y3', type is output
y3 = _LC5_A1;
-- Node name is 'y4'
-- Equation name is 'y4', type is output
y4 = _LC7_A1;
-- Node name is 'y5'
-- Equation name is 'y5', type is output
y5 = _LC1_A1;
-- Node name is 'y6'
-- Equation name is 'y6', type is output
y6 = _LC2_A2;
-- Node name is ':375'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = LCELL( _EQ001);
_EQ001 = din1 & !din3
# din0 & din2 & !din3
# !din1 & !din2 & din3
# !din0 & !din2 & !din3;
-- Node name is ':408'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = LCELL( _EQ002);
_EQ002 = !din0 & !din1 & !din3
# !din1 & !din2
# din0 & din1 & !din3
# !din2 & !din3;
-- Node name is ':441'
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ003);
_EQ003 = !din1 & !din2
# din2 & !din3
# !din1 & !din3
# din0 & !din3;
-- Node name is ':474'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ004);
_EQ004 = !din0 & !din2 & !din3
# din1 & !din2 & !din3
# din0 & !din1 & din2 & !din3
# !din0 & din1 & !din3
# !din0 & !din1 & !din2
# !din1 & !din2 & din3;
-- Node name is ':507'
-- Equation name is '_LC3_A5', type is buried
_LC3_A5 = LCELL( _EQ005);
_EQ005 = !din0 & !din2 & !din3
# !din0 & !din1 & !din2
# !din0 & din1 & !din3;
-- Node name is ':540'
-- Equation name is '_LC1_A4', type is buried
_LC1_A4 = LCELL( _EQ006);
_EQ006 = !din0 & !din1 & !din3
# !din1 & din2 & !din3
# !din0 & din2 & !din3
# !din0 & !din1 & !din2
# !din1 & !din2 & din3;
-- Node name is ':575'
-- Equation name is '_LC4_A3', type is buried
_LC4_A3 = LCELL( _EQ007);
_EQ007 = din1 & !din2 & !din3
# !din1 & din2 & !din3
# !din0 & din1 & !din3
# !din1 & !din2 & din3;
Project Information c:\clock_second\bcd_decoder.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,356K
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