📄 count_10.rpt
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Device-Specific Information: c:\clock_second\count_10.rpt
count_10
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 01 SOFT s ! 1 0 0 1 clr~1
- 2 - A 01 DFFE + 0 2 1 0 :3
- 6 - A 01 DFFE + 0 3 1 5 coun_103 (:9)
- 4 - A 01 DFFE + 0 3 1 3 coun_102 (:10)
- 3 - A 01 DFFE + 0 2 1 4 coun_101 (:11)
- 1 - A 01 DFFE + 0 3 1 5 coun_100 (:12)
- 5 - A 01 OR2 ! 0 4 0 2 :41
- 8 - A 01 OR2 0 4 0 1 :50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\clock_second\count_10.rpt
count_10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock_second\count_10.rpt
count_10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: c:\clock_second\count_10.rpt
count_10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 5 clr
Device-Specific Information: c:\clock_second\count_10.rpt
count_10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC7_A1, type is buried.
-- synthesized logic cell
!_LC7_A1 = _LC7_A1~NOT;
_LC7_A1~NOT = LCELL(!clr);
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC2_A1;
-- Node name is ':12' = 'coun_100'
-- Equation name is 'coun_100', location is LC1_A1, type is buried.
coun_100 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = coun_100 & coun_103 & !_LC5_A1
# !coun_100 & !_LC5_A1 & _LC8_A1;
-- Node name is ':11' = 'coun_101'
-- Equation name is 'coun_101', location is LC3_A1, type is buried.
coun_101 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !coun_100 & coun_101
# coun_100 & !coun_101 & !coun_103
# coun_101 & coun_103;
-- Node name is ':10' = 'coun_102'
-- Equation name is 'coun_102', location is LC4_A1, type is buried.
coun_102 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = !coun_101 & coun_102
# !coun_100 & coun_102
# coun_100 & coun_101 & !coun_102 & !coun_103
# coun_102 & coun_103;
-- Node name is ':9' = 'coun_103'
-- Equation name is 'coun_103', location is LC6_A1, type is buried.
coun_103 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = coun_100 & coun_101 & coun_102
# coun_102 & coun_103
# coun_101 & coun_103
# !coun_100 & coun_103;
-- Node name is 'qout0'
-- Equation name is 'qout0', type is output
qout0 = coun_100;
-- Node name is 'qout1'
-- Equation name is 'qout1', type is output
qout1 = coun_101;
-- Node name is 'qout2'
-- Equation name is 'qout2', type is output
qout2 = coun_102;
-- Node name is 'qout3'
-- Equation name is 'qout3', type is output
qout3 = coun_103;
-- Node name is ':3'
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = DFFE( _LC5_A1, GLOBAL( clk), VCC, VCC, !_LC7_A1);
-- Node name is ':41'
-- Equation name is '_LC5_A1', type is buried
!_LC5_A1 = _LC5_A1~NOT;
_LC5_A1~NOT = LCELL( _EQ005);
_EQ005 = coun_102
# coun_101
# !coun_103
# !coun_100;
-- Node name is ':50'
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ006);
_EQ006 = !coun_103
# !coun_100 & !coun_101 & !coun_102;
Project Information c:\clock_second\count_10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,815K
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