📄 clock_second.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
70 - - - 05 INPUT 0 0 0 1 clear
122 - - - 13 INPUT 0 0 0 1 clk
128 - - - 13 INPUT 0 0 0 3 fast_clk
95 - - B -- INPUT 0 0 0 1 stop
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\jinghua\clock_second.rpt
clock_second
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
43 - - - 18 OUTPUT 0 1 0 0 L0
44 - - - 18 OUTPUT 0 1 0 0 L1
46 - - - 17 OUTPUT 0 1 0 0 L2
47 - - - 16 OUTPUT 0 1 0 0 L3
48 - - - 15 OUTPUT 0 1 0 0 L4
49 - - - 14 OUTPUT 0 1 0 0 L5
51 - - - 14 OUTPUT 0 1 0 0 L6
8 - - A -- OUTPUT 0 1 0 0 seg0
102 - - A -- OUTPUT 0 1 0 0 seg1
100 - - A -- OUTPUT 0 1 0 0 seg2
99 - - B -- OUTPUT 0 1 0 0 seg3
97 - - B -- OUTPUT 0 1 0 0 seg4
96 - - B -- OUTPUT 0 1 0 0 seg5
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\jinghua\clock_second.rpt
clock_second
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - E 14 OR2 0 4 1 0 |BCD_DECODER:36|:375
- 2 - E 14 OR2 0 4 1 0 |BCD_DECODER:36|:408
- 3 - E 15 OR2 0 4 1 0 |BCD_DECODER:36|:441
- 6 - E 15 OR2 0 4 1 0 |BCD_DECODER:36|:474
- 2 - E 17 OR2 0 4 1 0 |BCD_DECODER:36|:507
- 4 - E 17 OR2 0 4 1 0 |BCD_DECODER:36|:540
- 8 - E 17 OR2 0 4 1 0 |BCD_DECODER:36|:575
- 2 - E 12 DFFE 0 3 0 5 |count_60:28|COUNT_6:2|:3
- 7 - E 12 DFFE 0 2 0 5 |count_60:28|COUNT_6:2|coun_63 (|count_60:28|COUNT_6:2|:9)
- 4 - E 12 DFFE 0 5 0 4 |count_60:28|COUNT_6:2|coun_62 (|count_60:28|COUNT_6:2|:10)
- 5 - E 12 DFFE 0 5 0 4 |count_60:28|COUNT_6:2|coun_61 (|count_60:28|COUNT_6:2|:11)
- 3 - E 12 DFFE 0 5 0 4 |count_60:28|COUNT_6:2|coun_60 (|count_60:28|COUNT_6:2|:12)
- 8 - E 12 AND2 0 4 0 1 |count_60:28|COUNT_6:2|:53
- 6 - E 12 DFFE 0 3 0 5 |count_60:28|COUNT_10:1|:3
- 5 - E 01 DFFE 0 5 0 6 |count_60:28|COUNT_10:1|coun_103 (|count_60:28|COUNT_10:1|:9)
- 3 - E 01 DFFE 0 5 0 4 |count_60:28|COUNT_10:1|coun_102 (|count_60:28|COUNT_10:1|:10)
- 4 - E 01 DFFE 0 4 0 5 |count_60:28|COUNT_10:1|coun_101 (|count_60:28|COUNT_10:1|:11)
- 8 - E 01 DFFE 0 5 0 6 |count_60:28|COUNT_10:1|coun_100 (|count_60:28|COUNT_10:1|:12)
- 1 - E 01 OR2 ! 0 4 0 2 |count_60:28|COUNT_10:1|:53
- 6 - E 01 OR2 0 4 0 1 |count_60:28|COUNT_10:1|:62
- 7 - E 06 DFFE 0 3 0 1 |count_60:29|COUNT_6:2|:3
- 2 - E 06 DFFE 0 2 0 5 |count_60:29|COUNT_6:2|coun_63 (|count_60:29|COUNT_6:2|:9)
- 5 - E 06 DFFE 0 5 0 4 |count_60:29|COUNT_6:2|coun_62 (|count_60:29|COUNT_6:2|:10)
- 1 - E 06 DFFE 0 5 0 4 |count_60:29|COUNT_6:2|coun_61 (|count_60:29|COUNT_6:2|:11)
- 4 - E 06 DFFE 0 5 0 4 |count_60:29|COUNT_6:2|coun_60 (|count_60:29|COUNT_6:2|:12)
- 6 - E 06 AND2 0 4 0 1 |count_60:29|COUNT_6:2|:53
- 1 - E 10 DFFE 0 3 0 5 |count_60:29|COUNT_10:1|:3
- 3 - E 10 DFFE 0 5 0 6 |count_60:29|COUNT_10:1|coun_103 (|count_60:29|COUNT_10:1|:9)
- 5 - E 10 DFFE 0 5 0 4 |count_60:29|COUNT_10:1|coun_102 (|count_60:29|COUNT_10:1|:10)
- 4 - E 10 DFFE 0 4 0 5 |count_60:29|COUNT_10:1|coun_101 (|count_60:29|COUNT_10:1|:11)
- 2 - E 10 DFFE 0 5 0 6 |count_60:29|COUNT_10:1|coun_100 (|count_60:29|COUNT_10:1|:12)
- 6 - E 10 OR2 ! 0 4 0 2 |count_60:29|COUNT_10:1|:53
- 7 - E 10 OR2 0 4 0 1 |count_60:29|COUNT_10:1|:62
- 5 - E 18 DFFE 0 3 0 5 |count_100:30|COUNT_10:9|:3
- 5 - E 20 DFFE 0 5 0 6 |count_100:30|COUNT_10:9|coun_103 (|count_100:30|COUNT_10:9|:9)
- 4 - E 20 DFFE 0 5 0 4 |count_100:30|COUNT_10:9|coun_102 (|count_100:30|COUNT_10:9|:10)
- 6 - E 20 DFFE 0 4 0 5 |count_100:30|COUNT_10:9|coun_101 (|count_100:30|COUNT_10:9|:11)
- 8 - E 20 DFFE 0 5 0 6 |count_100:30|COUNT_10:9|coun_100 (|count_100:30|COUNT_10:9|:12)
- 1 - E 20 AND2 0 4 0 2 |count_100:30|COUNT_10:9|:53
- 7 - E 20 OR2 0 4 0 1 |count_100:30|COUNT_10:9|:62
- 6 - E 18 DFFE 0 3 0 5 |count_100:30|COUNT_10:10|:3
- 2 - E 18 DFFE 0 5 0 6 |count_100:30|COUNT_10:10|coun_103 (|count_100:30|COUNT_10:10|:9)
- 1 - E 18 DFFE 0 5 0 4 |count_100:30|COUNT_10:10|coun_102 (|count_100:30|COUNT_10:10|:10)
- 4 - E 18 DFFE 0 4 0 5 |count_100:30|COUNT_10:10|coun_101 (|count_100:30|COUNT_10:10|:11)
- 7 - E 18 DFFE 0 5 0 6 |count_100:30|COUNT_10:10|coun_100 (|count_100:30|COUNT_10:10|:12)
- 3 - E 18 AND2 0 4 0 2 |count_100:30|COUNT_10:10|:53
- 8 - E 18 OR2 0 4 0 1 |count_100:30|COUNT_10:10|:62
- 7 - E 07 DFFE 1 3 0 8 |DISP_COUNT:31|coun_62 (|DISP_COUNT:31|:5)
- 5 - E 07 DFFE 1 3 0 8 |DISP_COUNT:31|coun_61 (|DISP_COUNT:31|:6)
- 2 - E 07 DFFE 1 3 0 8 |DISP_COUNT:31|coun_60 (|DISP_COUNT:31|:7)
- 6 - E 07 OR2 ! 0 3 1 7 |DISP_COUNT:31|:25
- 4 - E 02 OR2 0 4 0 1 |MUX_24_4:37|:77
- 1 - E 02 OR2 0 3 0 1 |MUX_24_4:37|:83
- 2 - E 01 OR2 0 3 0 1 |MUX_24_4:37|:89
- 4 - E 15 OR2 0 3 0 1 |MUX_24_4:37|:95
- 2 - E 15 OR2 0 3 0 7 |MUX_24_4:37|:101
- 3 - E 06 OR2 ! 0 4 0 1 |MUX_24_4:37|:110
- 5 - E 15 OR2 ! 0 3 0 1 |MUX_24_4:37|:113
- 7 - E 15 OR2 ! 0 3 0 1 |MUX_24_4:37|:116
- 8 - E 15 OR2 ! 0 3 0 1 |MUX_24_4:37|:119
- 1 - E 15 OR2 ! 0 3 0 7 |MUX_24_4:37|:122
- 3 - E 02 OR2 ! 0 4 0 1 |MUX_24_4:37|:131
- 1 - E 12 OR2 ! 0 3 0 1 |MUX_24_4:37|:134
- 3 - E 11 OR2 ! 0 3 0 1 |MUX_24_4:37|:137
- 1 - E 11 OR2 ! 0 3 0 1 |MUX_24_4:37|:140
- 2 - E 20 OR2 ! 0 3 0 7 |MUX_24_4:37|:143
- 5 - E 02 OR2 ! 0 4 0 1 |MUX_24_4:37|:152
- 2 - E 02 OR2 ! 0 3 0 1 |MUX_24_4:37|:155
- 7 - E 01 OR2 ! 0 3 0 1 |MUX_24_4:37|:158
- 2 - E 11 OR2 ! 0 3 0 1 |MUX_24_4:37|:161
- 3 - E 20 OR2 ! 0 3 0 7 |MUX_24_4:37|:164
- 4 - E 07 AND2 0 3 1 4 |SEG_SELECT:13|:162
- 1 - E 07 AND2 0 3 1 4 |SEG_SELECT:13|:172
- 6 - E 11 AND2 0 3 1 4 |SEG_SELECT:13|:182
- 3 - E 07 AND2 0 3 1 4 |SEG_SELECT:13|:192
- 8 - E 07 AND2 0 3 1 4 |SEG_SELECT:13|:202
- 8 - E 06 AND2 ! 1 1 0 30 :24
- 7 - B 20 OR2 2 0 0 5 |7400:33|1 (|7400:33|:4)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: c:\jinghua\clock_second.rpt
clock_second
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 1/ 96( 1%) 3/ 48( 6%) 1/ 48( 2%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 20/ 96( 20%) 23/ 48( 47%) 10/ 48( 20%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
14: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\jinghua\clock_second.rpt
clock_second
** CLOCK SIGNALS **
Type Fan-out Name
DFF 5 |count_60:28|COUNT_6:2|:3
DFF 5 |count_60:28|COUNT_10:1|:3
DFF 5 |count_60:29|COUNT_10:1|:3
DFF 5 |count_100:30|COUNT_10:9|:3
DFF 5 |count_100:30|COUNT_10:10|:3
LCELL 5 |7400:33|1
INPUT 3 fast_clk
Device-Specific Information: c:\jinghua\clock_second.rpt
clock_second
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 30 :24
Device-Specific Information: c:\jinghua\clock_second.rpt
clock_second
** EQUATIONS **
clear : INPUT;
clk : INPUT;
fast_clk : INPUT;
stop : INPUT;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = _LC8_E17;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC4_E17;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC2_E17;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC6_E15;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC3_E15;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC2_E14;
-- Node name is 'L6'
-- Equation name is 'L6', type is output
L6 = _LC1_E14;
-- Node name is 'seg0'
-- Equation name is 'seg0', type is output
seg0 = _LC8_E7;
-- Node name is 'seg1'
-- Equation name is 'seg1', type is output
seg1 = _LC3_E7;
-- Node name is 'seg2'
-- Equation name is 'seg2', type is output
seg2 = _LC6_E11;
-- Node name is 'seg3'
-- Equation name is 'seg3', type is output
seg3 = _LC1_E7;
-- Node name is 'seg4'
-- Equation name is 'seg4', type is output
seg4 = _LC4_E7;
-- Node name is 'seg5'
-- Equation name is 'seg5', type is output
seg5 = _LC6_E7;
-- Node name is '|BCD_DECODER:36|:375'
-- Equation name is '_LC1_E14', type is buried
_LC1_E14 = LCELL( _EQ001);
_EQ001 = _LC1_E15 & !_LC2_E15 & _LC3_E20
# !_LC2_E15 & _LC2_E20
# !_LC1_E15 & _LC2_E15 & !_LC2_E20
# !_LC1_E15 & !_LC2_E15 & !_LC3_E20;
-- Node name is '|BCD_DECODER:36|:408'
-- Equation name is '_LC2_E14', type is buried
_LC2_E14 = LCELL( _EQ002);
_EQ002 = !_LC1_E15 & !_LC2_E20
# !_LC2_E15 & _LC2_E20 & _LC3_E20
# !_LC2_E15 & !_LC2_E20 & !_LC3_E20
# !_LC1_E15 & !_LC2_E15;
-- Node name is '|BCD_DECODER:36|:441'
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