📄 count_60.rpt
字号:
Device-Specific Information: c:\clock_second\count_60.rpt
count_60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 5/ 48( 10%) 4/ 48( 8%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\clock_second\count_60.rpt
count_60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
DFF 5 |COUNT_10:1|:3
Device-Specific Information: c:\clock_second\count_60.rpt
count_60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 clr
Device-Specific Information: c:\clock_second\count_60.rpt
count_60
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC1_B4, type is buried.
-- synthesized logic cell
!_LC1_B4 = _LC1_B4~NOT;
_LC1_B4~NOT = LCELL(!clr);
-- Node name is 'co'
-- Equation name is 'co', type is output
co = _LC4_B7;
-- Node name is 'gewei0'
-- Equation name is 'gewei0', type is output
gewei0 = _LC2_B14;
-- Node name is 'gewei1'
-- Equation name is 'gewei1', type is output
gewei1 = _LC1_B14;
-- Node name is 'gewei2'
-- Equation name is 'gewei2', type is output
gewei2 = _LC6_B14;
-- Node name is 'gewei3'
-- Equation name is 'gewei3', type is output
gewei3 = _LC8_B14;
-- Node name is 'shiwei0'
-- Equation name is 'shiwei0', type is output
shiwei0 = _LC1_B7;
-- Node name is 'shiwei1'
-- Equation name is 'shiwei1', type is output
shiwei1 = _LC8_B7;
-- Node name is 'shiwei2'
-- Equation name is 'shiwei2', type is output
shiwei2 = _LC6_B7;
-- Node name is 'shiwei3'
-- Equation name is 'shiwei3', type is output
shiwei3 = _LC2_B7;
-- Node name is '|COUNT_6:2|:12' = '|COUNT_6:2|coun_60'
-- Equation name is '_LC1_B7', type is buried
_LC1_B7 = DFFE( _EQ001, _LC3_B7, GLOBAL(!clr), VCC, VCC);
_EQ001 = _LC1_B7 & _LC2_B7
# !_LC1_B7 & !_LC2_B7 & !_LC8_B7
# !_LC1_B7 & !_LC2_B7 & !_LC6_B7
# _LC1_B7 & _LC6_B7 & _LC8_B7;
-- Node name is '|COUNT_6:2|:11' = '|COUNT_6:2|coun_61'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = DFFE( _EQ002, _LC3_B7, GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC1_B7 & _LC8_B7
# _LC1_B7 & !_LC2_B7 & !_LC6_B7 & !_LC8_B7
# _LC6_B7 & _LC8_B7
# _LC2_B7 & _LC8_B7;
-- Node name is '|COUNT_6:2|:10' = '|COUNT_6:2|coun_62'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = DFFE( _EQ003, _LC3_B7, GLOBAL(!clr), VCC, VCC);
_EQ003 = _LC2_B7 & _LC6_B7
# _LC1_B7 & !_LC2_B7 & _LC8_B7
# _LC6_B7 & _LC8_B7
# !_LC1_B7 & _LC6_B7;
-- Node name is '|COUNT_6:2|:9' = '|COUNT_6:2|coun_63'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = DFFE( _LC2_B7, _LC3_B7, GLOBAL(!clr), VCC, VCC);
-- Node name is '|COUNT_6:2|:3'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = DFFE( _LC5_B7, _LC3_B7, VCC, VCC, !_LC1_B4);
-- Node name is '|COUNT_6:2|:53'
-- Equation name is '_LC5_B7', type is buried
_LC5_B7 = LCELL( _EQ004);
_EQ004 = _LC1_B7 & !_LC2_B7 & _LC6_B7 & !_LC8_B7;
-- Node name is '|COUNT_10:1|:12' = '|COUNT_10:1|coun_100'
-- Equation name is '_LC2_B14', type is buried
_LC2_B14 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = _LC2_B14 & !_LC4_B14 & _LC8_B14
# !_LC2_B14 & _LC3_B14 & !_LC4_B14;
-- Node name is '|COUNT_10:1|:11' = '|COUNT_10:1|coun_101'
-- Equation name is '_LC1_B14', type is buried
_LC1_B14 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = _LC1_B14 & !_LC2_B14
# !_LC1_B14 & _LC2_B14 & !_LC8_B14
# _LC1_B14 & _LC8_B14;
-- Node name is '|COUNT_10:1|:10' = '|COUNT_10:1|coun_102'
-- Equation name is '_LC6_B14', type is buried
_LC6_B14 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ007 = !_LC1_B14 & _LC6_B14
# !_LC2_B14 & _LC6_B14
# _LC1_B14 & _LC2_B14 & !_LC6_B14 & !_LC8_B14
# _LC6_B14 & _LC8_B14;
-- Node name is '|COUNT_10:1|:9' = '|COUNT_10:1|coun_103'
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ008 = !_LC2_B14 & _LC8_B14
# _LC1_B14 & _LC2_B14 & _LC6_B14
# _LC6_B14 & _LC8_B14
# _LC1_B14 & _LC8_B14;
-- Node name is '|COUNT_10:1|:3'
-- Equation name is '_LC3_B7', type is buried
_LC3_B7 = DFFE( _LC4_B14, GLOBAL( clk), VCC, VCC, !_LC1_B4);
-- Node name is '|COUNT_10:1|:53'
-- Equation name is '_LC4_B14', type is buried
!_LC4_B14 = _LC4_B14~NOT;
_LC4_B14~NOT = LCELL( _EQ009);
_EQ009 = !_LC8_B14
# !_LC2_B14
# _LC6_B14
# _LC1_B14;
-- Node name is '|COUNT_10:1|:62'
-- Equation name is '_LC3_B14', type is buried
_LC3_B14 = LCELL( _EQ010);
_EQ010 = !_LC8_B14
# !_LC1_B14 & !_LC2_B14 & !_LC6_B14;
Project Information c:\clock_second\count_60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,003K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -