mux_6_1.rpt

多功能秒表的设计

         #  count_flag0 &  data_smin3;

-- Node name is ':83' 
-- Equation name is '_LC4_A3', type is buried 
_LC4_A3  = LCELL( _EQ007);
  _EQ007 =  data_ssec3 &  _LC1_A8
         # !_LC1_A8 &  _LC3_A3
         # !_LC1_A8 &  _LC2_A3;

-- Node name is ':89' 
-- Equation name is '_LC5_A3', type is buried 
_LC5_A3  = LCELL( _EQ008);
  _EQ008 =  _LC4_A3 & !_LC4_A7
         #  data_gsec3 &  _LC4_A7;

-- Node name is ':95' 
-- Equation name is '_LC6_A3', type is buried 
_LC6_A3  = LCELL( _EQ009);
  _EQ009 = !_LC2_A5 &  _LC5_A3
         #  data_smm3 &  _LC2_A5;

-- Node name is ':101' 
-- Equation name is '_LC1_A3', type is buried 
_LC1_A3  = LCELL( _EQ010);
  _EQ010 = !_LC2_A6 &  _LC6_A3
         #  data_gmm3 &  _LC2_A6;

-- Node name is ':111' 
-- Equation name is '_LC3_A2', type is buried 
_LC3_A2  = LCELL( _EQ011);
  _EQ011 = !count_flag0 & !count_flag1 &  count_flag2 &  data_gmin2;

-- Node name is ':112' 
-- Equation name is '_LC4_A2', type is buried 
_LC4_A2  = LCELL( _EQ012);
  _EQ012 =  count_flag1
         # !count_flag2
         #  count_flag0 &  data_smin2;

-- Node name is ':113' 
-- Equation name is '_LC5_A2', type is buried 
_LC5_A2  = LCELL( _EQ013);
  _EQ013 =  data_ssec2 &  _LC1_A8
         # !_LC1_A8 &  _LC4_A2
         # !_LC1_A8 &  _LC3_A2;

-- Node name is ':116' 
-- Equation name is '_LC6_A2', type is buried 
_LC6_A2  = LCELL( _EQ014);
  _EQ014 = !_LC4_A7 &  _LC5_A2
         #  data_gsec2 &  _LC4_A7;

-- Node name is ':119' 
-- Equation name is '_LC2_A2', type is buried 
_LC2_A2  = LCELL( _EQ015);
  _EQ015 = !_LC2_A5 &  _LC6_A2
         #  data_smm2 &  _LC2_A5;

-- Node name is ':122' 
-- Equation name is '_LC1_A2', type is buried 
_LC1_A2  = LCELL( _EQ016);
  _EQ016 =  _LC2_A2 & !_LC2_A6
         #  data_gmm2 &  _LC2_A6;

-- Node name is ':132' 
-- Equation name is '_LC6_A4', type is buried 
_LC6_A4  = LCELL( _EQ017);
  _EQ017 = !count_flag0 & !count_flag1 &  count_flag2 &  data_gmin1;

-- Node name is ':133' 
-- Equation name is '_LC2_A4', type is buried 
_LC2_A4  = LCELL( _EQ018);
  _EQ018 =  count_flag1
         # !count_flag2
         #  count_flag0 &  data_smin1;

-- Node name is ':134' 
-- Equation name is '_LC3_A4', type is buried 
_LC3_A4  = LCELL( _EQ019);
  _EQ019 =  data_ssec1 &  _LC1_A8
         # !_LC1_A8 &  _LC2_A4
         # !_LC1_A8 &  _LC6_A4;

-- Node name is ':137' 
-- Equation name is '_LC4_A4', type is buried 
_LC4_A4  = LCELL( _EQ020);
  _EQ020 =  _LC3_A4 & !_LC4_A7
         #  data_gsec1 &  _LC4_A7;

-- Node name is ':140' 
-- Equation name is '_LC5_A4', type is buried 
_LC5_A4  = LCELL( _EQ021);
  _EQ021 = !_LC2_A5 &  _LC4_A4
         #  data_smm1 &  _LC2_A5;

-- Node name is ':143' 
-- Equation name is '_LC1_A4', type is buried 
_LC1_A4  = LCELL( _EQ022);
  _EQ022 = !_LC2_A6 &  _LC5_A4
         #  data_gmm1 &  _LC2_A6;

-- Node name is ':153' 
-- Equation name is '_LC1_A1', type is buried 
_LC1_A1  = LCELL( _EQ023);
  _EQ023 = !count_flag0 & !count_flag1 &  count_flag2 &  data_gmin0;

-- Node name is ':154' 
-- Equation name is '_LC3_A1', type is buried 
_LC3_A1  = LCELL( _EQ024);
  _EQ024 =  count_flag1
         # !count_flag2
         #  count_flag0 &  data_smin0;

-- Node name is ':155' 
-- Equation name is '_LC4_A1', type is buried 
_LC4_A1  = LCELL( _EQ025);
  _EQ025 =  data_ssec0 &  _LC1_A8
         # !_LC1_A8 &  _LC3_A1
         #  _LC1_A1 & !_LC1_A8;

-- Node name is ':158' 
-- Equation name is '_LC5_A1', type is buried 
_LC5_A1  = LCELL( _EQ026);
  _EQ026 =  _LC4_A1 & !_LC4_A7
         #  data_gsec0 &  _LC4_A7;

-- Node name is ':161' 
-- Equation name is '_LC6_A1', type is buried 
_LC6_A1  = LCELL( _EQ027);
  _EQ027 = !_LC2_A5 &  _LC5_A1
         #  data_smm0 &  _LC2_A5;

-- Node name is ':164' 
-- Equation name is '_LC2_A1', type is buried 
_LC2_A1  = LCELL( _EQ028);
  _EQ028 = !_LC2_A6 &  _LC6_A1
         #  data_gmm0 &  _LC2_A6;



Project Information                                c:\clock_second\mux_6_1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:02
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 18,054K