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📄 mux_6_1.rpt

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 117      -     -    -    05      INPUT                0    0    0    1  data_gsec0
 110      -     -    -    01      INPUT                0    0    0    1  data_gsec1
 111      -     -    -    01      INPUT                0    0    0    1  data_gsec2
 125      -     -    -    --      INPUT                0    0    0    1  data_gsec3
  55      -     -    -    --      INPUT                0    0    0    1  data_smin0
 143      -     -    A    --      INPUT                0    0    0    1  data_smin1
 144      -     -    A    --      INPUT                0    0    0    1  data_smin2
   7      -     -    A    --      INPUT                0    0    0    1  data_smin3
   8      -     -    A    --      INPUT                0    0    0    1  data_smm0
 109      -     -    A    --      INPUT                0    0    0    1  data_smm1
 101      -     -    A    --      INPUT                0    0    0    1  data_smm2
 102      -     -    A    --      INPUT                0    0    0    1  data_smm3
 100      -     -    A    --      INPUT                0    0    0    1  data_ssec0
 112      -     -    -    02      INPUT                0    0    0    1  data_ssec1
  56      -     -    -    --      INPUT                0    0    0    1  data_ssec2
  72      -     -    -    03      INPUT                0    0    0    1  data_ssec3


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                       c:\clock_second\mux_6_1.rpt
mux_6_1

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
  87      -     -    E    --     OUTPUT                0    1    0    0  bcd_out0
  98      -     -    B    --     OUTPUT                0    1    0    0  bcd_out1
  81      -     -    F    --     OUTPUT                0    1    0    0  bcd_out2
  99      -     -    B    --     OUTPUT                0    1    0    0  bcd_out3


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:                       c:\clock_second\mux_6_1.rpt
mux_6_1

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      2     -    A    06       AND2                3    0    0    4  :38
   -      2     -    A    05       AND2                3    0    0    4  :42
   -      4     -    A    07       AND2                3    0    0    4  :46
   -      1     -    A    08        OR2        !       3    0    0    4  :50
   -      2     -    A    03       AND2                4    0    0    1  :78
   -      3     -    A    03        OR2                4    0    0    1  :79
   -      4     -    A    03        OR2                1    3    0    1  :83
   -      5     -    A    03        OR2                1    2    0    1  :89
   -      6     -    A    03        OR2                1    2    0    1  :95
   -      1     -    A    03        OR2                1    2    1    0  :101
   -      3     -    A    02       AND2                4    0    0    1  :111
   -      4     -    A    02        OR2                4    0    0    1  :112
   -      5     -    A    02        OR2                1    3    0    1  :113
   -      6     -    A    02        OR2                1    2    0    1  :116
   -      2     -    A    02        OR2                1    2    0    1  :119
   -      1     -    A    02        OR2                1    2    1    0  :122
   -      6     -    A    04       AND2                4    0    0    1  :132
   -      2     -    A    04        OR2                4    0    0    1  :133
   -      3     -    A    04        OR2                1    3    0    1  :134
   -      4     -    A    04        OR2                1    2    0    1  :137
   -      5     -    A    04        OR2                1    2    0    1  :140
   -      1     -    A    04        OR2                1    2    1    0  :143
   -      1     -    A    01       AND2                4    0    0    1  :153
   -      3     -    A    01        OR2                4    0    0    1  :154
   -      4     -    A    01        OR2                1    3    0    1  :155
   -      5     -    A    01        OR2                1    2    0    1  :158
   -      6     -    A    01        OR2                1    2    0    1  :161
   -      2     -    A    01        OR2                1    2    1    0  :164


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:                       c:\clock_second\mux_6_1.rpt
mux_6_1

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       8/ 96(  8%)    17/ 48( 35%)     0/ 48(  0%)    8/16( 50%)      0/16(  0%)     0/16(  0%)
B:       0/ 96(  0%)     2/ 48(  4%)     0/ 48(  0%)    0/16(  0%)      2/16( 12%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
D:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
E:       0/ 96(  0%)     1/ 48(  2%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)
F:       0/ 96(  0%)     1/ 48(  2%)     0/ 48(  0%)    0/16(  0%)      1/16(  6%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      4/24( 16%)     3/4( 75%)      0/4(  0%)       0/4(  0%)
02:      2/24(  8%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
03:      4/24( 16%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
04:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
05:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
06:      1/24(  4%)     1/4( 25%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      2/24(  8%)     2/4( 50%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:                       c:\clock_second\mux_6_1.rpt
mux_6_1

** EQUATIONS **

count_flag0 : INPUT;
count_flag1 : INPUT;
count_flag2 : INPUT;
data_gmin0 : INPUT;
data_gmin1 : INPUT;
data_gmin2 : INPUT;
data_gmin3 : INPUT;
data_gmm0 : INPUT;
data_gmm1 : INPUT;
data_gmm2 : INPUT;
data_gmm3 : INPUT;
data_gsec0 : INPUT;
data_gsec1 : INPUT;
data_gsec2 : INPUT;
data_gsec3 : INPUT;
data_smin0 : INPUT;
data_smin1 : INPUT;
data_smin2 : INPUT;
data_smin3 : INPUT;
data_smm0 : INPUT;
data_smm1 : INPUT;
data_smm2 : INPUT;
data_smm3 : INPUT;
data_ssec0 : INPUT;
data_ssec1 : INPUT;
data_ssec2 : INPUT;
data_ssec3 : INPUT;

-- Node name is 'bcd_out0' 
-- Equation name is 'bcd_out0', type is output 
bcd_out0 =  _LC2_A1;

-- Node name is 'bcd_out1' 
-- Equation name is 'bcd_out1', type is output 
bcd_out1 =  _LC1_A4;

-- Node name is 'bcd_out2' 
-- Equation name is 'bcd_out2', type is output 
bcd_out2 =  _LC1_A2;

-- Node name is 'bcd_out3' 
-- Equation name is 'bcd_out3', type is output 
bcd_out3 =  _LC1_A3;

-- Node name is ':38' 
-- Equation name is '_LC2_A6', type is buried 
_LC2_A6  = LCELL( _EQ001);
  _EQ001 = !count_flag0 & !count_flag1 & !count_flag2;

-- Node name is ':42' 
-- Equation name is '_LC2_A5', type is buried 
_LC2_A5  = LCELL( _EQ002);
  _EQ002 =  count_flag0 & !count_flag1 & !count_flag2;

-- Node name is ':46' 
-- Equation name is '_LC4_A7', type is buried 
_LC4_A7  = LCELL( _EQ003);
  _EQ003 = !count_flag0 &  count_flag1 & !count_flag2;

-- Node name is ':50' 
-- Equation name is '_LC1_A8', type is buried 
!_LC1_A8 = _LC1_A8~NOT;
_LC1_A8~NOT = LCELL( _EQ004);
  _EQ004 =  count_flag2
         # !count_flag1
         # !count_flag0;

-- Node name is ':78' 
-- Equation name is '_LC2_A3', type is buried 
_LC2_A3  = LCELL( _EQ005);
  _EQ005 = !count_flag0 & !count_flag1 &  count_flag2 &  data_gmin3;

-- Node name is ':79' 
-- Equation name is '_LC3_A3', type is buried 
_LC3_A3  = LCELL( _EQ006);
  _EQ006 =  count_flag1
         # !count_flag2

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