9536.vhd

来自「FIFO和计数器以及时钟控制」· VHDL 代码 · 共 52 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity 9536 is
port(XF:IN STD_LOGIC;  --P13
     CLR:IN STD_LOGIC; --P39
	MTRB:IN STD_LOGIC;--P8
	PS:IN STD_LOGIC;  --P11
	DS:IN STD_LOGIC;  --P1
	A19:IN STD_LOGIC; --P43
	DSP_RW:IN STD_LOGIC; --P12
	RW_O:OUT STD_LOGIC;	 --P38
	FLASH_CE:OUT STD_LOGIC; --P34
	INV_RW:OUT STD_LOGIC;   --P37
	FLASH_OE:OUT STD_LOGIC; --P35
	FLASH_WE:OUT STD_LOGIC --P14
	);

end 9536;

architecture Behavioral of 9536 is

begin
	RW_O<=DSP_RW;
	INV_RW<=NOT DSP_RW;
	FLASH_OE<=NOT DSP_RW;
	FLASH_WE<= DSP_RW;
	CASE XF IS
	WHEN '1'=>
	    IF CLR='0' THEN
	        FLASH_CE<=DS OR MSTRB;
         ELSE
	        FLASH_CE<='0';
         END IF;
     WHEN '0'=>
	    IF CLR='0' THEN
             FLASH_CE<=PS OR MSTRB OR (NOT A19);
	    ELSE
		   FLASH_CE<='0';
	    END IF;
	 WHEN OTHERS=>FLASH_CE<='0';
	 END CASE;

end Behavioral;