communication.vhd

FIFO和计数器以及时钟控制

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity communication is
    port(
          clr: in std_logic;
          clk_uart: in std_logic;	   --100M: 115200bps
          txd : out std_logic;
          rxd: in std_logic;
			 uart_data_in : in std_logic_vector(7 downto 0);
			 uart_data_out : out std_logic_vector(7 downto 0);
			 connect_pc : out std_logic;
			 uart_int:out std_logic;
			 uart_tx_busy: out std_logic;
          uart_tx_fifo_wrcs : in std_logic;
			 uart_rx_fifo_rdcs : in std_logic;
    -- dsp connection port
          dsp_rw: in std_logic

);
end communication;

architecture rtl of communication is

component uart_port
    Port ( data_in : in std_logic_vector(7 downto 0);
           wr : in std_logic;
           clk_uart : in std_logic;
           clr : in std_logic;
			  tx_busy_out : out std_logic;
           uart_tx_fifo_wrcs : in std_logic;
			  uart_rx_fifo_rdcs : in std_logic;
           rxd : in std_logic;
           txd : out std_logic;
			  connect_pc : out std_logic;
			  uart_int:out std_logic;
           data_out : out std_logic_vector(7 downto 0)
			  );
end component ;
signal clk_uart_2: std_logic;

begin


process(clk_uart,clr)
begin
if clr ='1' then
	clk_uart_2 <= '0';
elsif rising_edge (clk_uart) then
	clk_uart_2 <= not clk_uart_2;
end if;
end process;

u1_uart:uart_port
Port map(
           data_in => uart_data_in,
           wr => dsp_rw,
           clk_uart => clk_uart_2,
           clr => clr,
           uart_tx_fifo_wrcs => uart_tx_fifo_wrcs ,
			  uart_rx_fifo_rdcs => uart_rx_fifo_rdcs,
           rxd => rxd,
           txd => txd,
			  tx_busy_out => uart_tx_busy,
			  uart_int => uart_int,
			  connect_pc => connect_pc,
           data_out => uart_data_out 
         );
end rtl;