afifo127s8_ip.vhd

FIFO和计数器以及时钟控制

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity afifo127s8_ip is
port(
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	wr_clk: IN std_logic;
	rd_en: IN std_logic;
	rd_clk: IN std_logic;
	ainit: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic);


end afifo127s8_ip;

architecture a of afifo127s8_ip is
component afifo127_s8
	port (
	din: IN std_logic_VECTOR(7 downto 0);
	wr_en: IN std_logic;
	wr_clk: IN std_logic;
	rd_en: IN std_logic;
	rd_clk: IN std_logic;
	ainit: IN std_logic;
	dout: OUT std_logic_VECTOR(7 downto 0);
	full: OUT std_logic;
	empty: OUT std_logic);
end component;

--2004/07/19 modified
component up_dn
port ( clk,clr,din: in std_logic;
        up: out std_logic);
end component;
--end modified

signal wr,rd : std_logic;
begin

u1: afifo127_s8
port map(
          din=> din,
			 wr_en => wr,
			 wr_clk => wr_clk,
			 rd_en => rd,
			 rd_clk => rd_clk,
			 ainit => ainit,
			 dout => dout,
			 full => full,
			 empty	 => empty
);

--2004/07/19 modified

--tt:block
--signal t1,t2,t3,t4 : std_logic;
--begin
--p1:process(wr_clk, ainit )	
--begin
--if ainit = '1' then
--	t1<='0';
--	t2<='0';
--elsif rising_edge( wr_clk) then
--	t1<= wr_en;
--	if wr_en ='1' and t1 ='0' then
--		t2 <='1';
--	else
--		t2 <= '0';
--	end if;
--end if;
--end process p1;
--wr <= t2;
--p2:process(rd_clk, ainit )	
--begin
--if ainit = '1' then
--	t3<='0';
--	t4<='0';
--elsif rising_edge( rd_clk) then
--	t3<= rd_en;
--	if rd_en ='1' and t3 ='0' then
--		t4 <='1';
--	else
--		t4 <= '0';
--	end if;
--end if;
--end process p2;
--rd <= t4;
--end block tt;

gen_fifo_rd: up_dn
port map ( clk => rd_clk,
           clr => ainit,
           din => rd_en,
           up  => RD
           );
gen_fifo_wr: up_dn
port map ( clk => wr_clk,
           clr => ainit,
           din => wr_en,
           up  => WR
           );

--end modified

end a;