clock_div.vhd

来自「FIFO和计数器以及时钟控制」· VHDL 代码 · 共 58 行

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--
-- Title       : clock_div
-- Design      : RC_CKJH
-- Author      : 杨云龙
-- Company     : 北京百科融创科技有限公司
--
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--
-- File        : clock_div.vhd
-- Generated   : Tue Nov 11 10:28:46 2003
-- From        : interface description file
-- By          : Itf2Vhdl ver. 1.20
--
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--
-- Description : 
--
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--{{ Section below this comment is automatically maintained
--   and may be overwritten
--{entity {lcd_port} architecture {a}}

	library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity clock_div is
	port
	(
	clk1,clk2,clr1,clr2:in std_logic;
	qa :out std_logic_vector( 3 downto 0);
	qb :out std_logic_vector(3 downto 0));
end clock_div;

architecture a of clock_div is
signal tempa,tempb:std_logic_vector(3 downto 0);
begin
p1:	process (clk1,clr1,tempa)
	begin
		if clr1='1' then
			tempa<="0000";
		elsif falling_edge(clk1) then
			tempa<=tempa+1;
		end if;	
		qa<=tempa;
end process p1;
p2:	process (clk2,clr2,tempb)
	begin
		if clr2='1' then
			tempb<="0000";
		elsif falling_edge(clk2) then
			tempb<=tempb+1;
		end if;
	qb<=tempb;
end process p2;
end a;