ad_ctl_tb.vhd

FIFO和计数器以及时钟控制

-- VHDL Test Bench Created from source file ad_control.vhd -- 12:38:07 02/08/2004
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY ad_control_ad_ctl_tb_vhd_tb IS
END ad_control_ad_ctl_tb_vhd_tb;

ARCHITECTURE behavior OF ad_control_ad_ctl_tb_vhd_tb IS 

	COMPONENT ad_control
	PORT(
		CLK_AD : IN std_logic;
		RESET : IN std_logic;
		AD1_OUT : IN std_logic;
		AD1_CS : IN std_logic;
		AD2_OUT : IN std_logic;
		AD2_CS : IN std_logic;
		AD3_OUT : IN std_logic;
		AD3_CS : IN std_logic;
		AD4_OUT : IN std_logic;
		AD4_CS : IN std_logic;
		AD5_OUT : IN std_logic;
		AD5_CS : IN std_logic;
		AD_FIFO_RDCLOCK : IN std_logic;
		AD_FIFO_RD : IN std_logic;
		AD_FIFO_RDCS : IN std_logic_vector(4 downto 0);          
		AD_CLK : OUT std_logic;
		AD1_DATA : OUT std_logic_vector(7 downto 0);
		AD2_DATA : OUT std_logic_vector(7 downto 0);
		AD3_DATA : OUT std_logic_vector(7 downto 0);
		AD4_DATA : OUT std_logic_vector(7 downto 0);
		AD5_DATA : OUT std_logic_vector(7 downto 0);
		AD_FLAG : OUT std_logic_vector(4 downto 0)
		);
	END COMPONENT;

	SIGNAL CLK_AD :  std_logic;
	SIGNAL AD_CLK :  std_logic;
	SIGNAL RESET :  std_logic;
	SIGNAL AD1_OUT :  std_logic;
	SIGNAL AD1_CS :  std_logic;
	SIGNAL AD1_DATA :  std_logic_vector(7 downto 0);
	SIGNAL AD2_OUT :  std_logic;
	SIGNAL AD2_CS :  std_logic;
	SIGNAL AD2_DATA :  std_logic_vector(7 downto 0);
	SIGNAL AD3_OUT :  std_logic;
	SIGNAL AD3_CS :  std_logic;
	SIGNAL AD3_DATA :  std_logic_vector(7 downto 0);
	SIGNAL AD4_OUT :  std_logic;
	SIGNAL AD4_CS :  std_logic;
	SIGNAL AD4_DATA :  std_logic_vector(7 downto 0);
	SIGNAL AD5_OUT :  std_logic;
	SIGNAL AD5_CS :  std_logic;
	SIGNAL AD5_DATA :  std_logic_vector(7 downto 0);
	SIGNAL AD_FIFO_RDCLOCK :  std_logic;
	SIGNAL AD_FIFO_RD :  std_logic;
	SIGNAL AD_FIFO_RDCS :  std_logic_vector(4 downto 0);
	SIGNAL AD_FLAG :  std_logic_vector(4 downto 0);
 	signal end_sim:bit:='0';

BEGIN

	uut: ad_control PORT MAP(
		CLK_AD => CLK_AD,
		AD_CLK => AD_CLK,
		RESET => RESET,
		AD1_OUT => AD1_OUT,
		AD1_CS => AD1_CS,
		AD1_DATA => AD1_DATA,
		AD2_OUT => AD2_OUT,
		AD2_CS => AD2_CS,
		AD2_DATA => AD2_DATA,
		AD3_OUT => AD3_OUT,
		AD3_CS => AD3_CS,
		AD3_DATA => AD3_DATA,
		AD4_OUT => AD4_OUT,
		AD4_CS => AD4_CS,
		AD4_DATA => AD4_DATA,
		AD5_OUT => AD5_OUT,
		AD5_CS => AD5_CS,
		AD5_DATA => AD5_DATA,
		AD_FIFO_RDCLOCK => AD_FIFO_RDCLOCK,
		AD_FIFO_RD => AD_FIFO_RD,
		AD_FIFO_RDCS => AD_FIFO_RDCS,
		AD_FLAG => AD_FLAG
	);


-- *** Test Bench - User Defined Section ***
CLK_GEN:PROCESS	   
BEGIN
	IF END_SIM='0' THEN
		CLK_AD<='0';
		WAIT FOR 7.8125 us;
		CLK_AD<='1';
		WAIT FOR 7.8125 us;
	ELSE
		NULL;
	END IF;	
END PROCESS CLK_GEN;  

RDCLK_GEN:PROCESS	   
BEGIN
	IF END_SIM='0' THEN
		AD_FIFO_RDCLOCK<='0';
		WAIT FOR 10 ns;
		AD_FIFO_RDCLOCK<='1';
		WAIT FOR 10 ns;
	ELSE
		NULL;
	END IF;	
END PROCESS RDCLK_GEN; 

RD_GEN:PROCESS(AD_FIFO_RDCS,AD_FIFO_RDCLOCK)	   
BEGIN
	IF AD_FIFO_RDCS ="00000" THEN
		if falling_edge (AD_FIFO_RDCLOCK) then
			AD_FIFO_RD<=not ad_fifo_rd;
		ELSE 
			AD_FIFO_RD<= ad_fifo_rd;
		end if;
	else
		AD_FIFO_RD <='0';
	END IF;	
END PROCESS RD_GEN; 

da_input:process
begin		
	IF END_SIM='0' THEN
		AD1_OUT<='0'; 
		AD2_OUT<='1'; 
		AD3_OUT<='0'; 
		AD4_OUT<='1';
		AD5_OUT<='0';
		WAIT FOR 78.125 us;
		AD1_OUT<='1';
		AD2_OUT<='0';
		AD3_OUT<='1';
		AD4_OUT<='0';
		AD5_OUT<='1';
		WAIT FOR 78.125 us;
	ELSE
		NULL;
	END IF;	
end process da_input;
PROCESS
BEGIN		
	RESET <='1';
	AD1_CS<='1';
	AD2_CS<='1';
	AD3_CS<='1';
	AD4_CS<='1';
	AD5_CS<='1';
	AD_FIFO_RDCS <= "11111";
	WAIT FOR 8 us;
	RESET <='0';
	AD1_CS<='0';
	AD2_CS<='0';
	AD3_CS<='0';
	AD4_CS<='0';
	AD5_CS<='0';  
	wait until ad_flag ="11111";
	AD_FIFO_RDCS<="00000" ;
	WAIT until ad_flag ="00000";
	ad_fifo_rdcs <= "11111";
	wait until ad_flag ="11111";
	AD_FIFO_RDCS<="00000" ;
	WAIT until ad_flag ="00000";
	ad_fifo_rdcs <= "11111";
END PROCESS;
-- *** End Test Bench - User Defined Section ***

END;