com_min.vhd

来自「FIFO和计数器以及时钟控制」· VHDL 代码 · 共 53 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity com_min is
  port (
    MIN_DATA : out STD_LOGIC_VECTOR(7 downto 0);
    D_A : in STD_LOGIC_VECTOR(7 downto 0);
    clk : in std_logic;
    D_B : in STD_LOGIC_VECTOR(7 downto 0)
  );
end com_min;

architecture compare_arch of com_min is

signal sym_a,sym_b : std_logic;
signal ta ,tb : std_logic_vector(6 downto 0);

begin

sym_a <= d_a(7);
sym_b <= d_b(7);
ta <= d_a(6 downto 0);
tb <= d_b(6 downto 0);
process(clk,ta,tb,sym_a,sym_b)
begin
if rising_edge(clk) then
if sym_a < sym_b then
  min_data <= d_b;
elsif sym_a > sym_b then
  min_data <= d_a;
elsif ((sym_a and sym_b) ='1') then
  if ((UNSIGNED(ta) > UNSIGNED(tb)) or ((UNSIGNED(ta) = UNSIGNED(tb)))) then
    min_data <= d_a;
  else
    min_data <= d_b;
  end if;
elsif ((sym_a or sym_b) ='0') then
   if ((UNSIGNED(ta) > UNSIGNED(tb)) or ((UNSIGNED(ta) = UNSIGNED(tb)))) then
    min_data <= d_b;
  else
    min_data <= d_a;
  end if;
end if;
end if;
end process; 
end architecture compare_arch;