add_sub_12.vhd

来自「FIFO和计数器以及时钟控制」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity add_sub_12 is
port(
clk : in std_logic;
aclr : in std_logic;
add : in std_logic;
a : in std_logic_vector(6 downto 0);
b : in std_logic_vector(6 downto 0);
q_c_out : out std_logic;
q : out std_logic_vector(6 downto 0)
);
end add_sub_12;

architecture a of add_sub_12 is

begin
process(aclr,clk)
variable qa : std_logic_vector(7 downto 0);
variable qb : std_logic_vector(6 downto 0);
variable q_c : std_logic;
begin
if aclr='1' then
  qa:=(others=>'0');
  q_c:='0';
elsif rising_edge(clk) then
  if add='1' then
    qa := ('0' & a)+b;
    q_c := qa(7);
  else
    qa := ('0' & a)-b;
    q_c := qa(7);
  end if;
    if add='0' and q_c='1' then
      qb := (not qa(6 downto 0))+'1';
    else
      qb := qa(6 downto 0);
    end if;

end if;
q<= qb;
q_c_out <= q_c;
end process;
end a;