counter.vhd

来自「FIFO和计数器以及时钟控制」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
	port(clk,clr:in std_logic;
		q:out std_logic);
end counter;

architecture a of counter is
	signal qq:std_logic_vector(2 downto 0);
begin
process(clk,clr)
begin
	if clr='1' then
		qq<=(others=>'0');
		q<='0';
	elsif rising_edge(clk)then
		if qq="111"then
			qq<="000";
			q<='1';
		else 
			qq<=qq+1;
			q<='0';
		end if;
	end if;
end process;
end a;