clk_gen_block.vhdl

FIFO和计数器以及时钟控制

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_gen_block is
    Port ( dsp_clk_in : in std_logic;
           clr : in std_logic;
           dsp_clk_divout: out std_logic;
           clk_480k : out std_logic;
           clk_160k : out std_logic
    );
end clk_gen_block;

architecture Behavioral of clk_gen_block is

signal clk_16800k : std_logic;--16M
signal CLK_10000K : std_logic;--8M
signal CLK_480K_TMP : std_logic;  --480K

component div_clk
  PORT(
    CLK, CLR: IN  STD_LOGIC;
    Q5 : OUT  STD_LOGIC);
end component;

begin

dsp_clk_div5 : div_clk
port map(
    CLK=>  dsp_clk_in,
    CLR => clr,
    Q5 => clk_16800k    --16M
);

process(clr,clk_16800k)
variable cta : integer range 0 to 34;
begin
if clr ='1' then
  cta :=0;
elsif rising_edge(clk_16800k) then
  if cta = 34 then
     cta :=0;
     clk_480k_TMP <='1';
  else
     cta := cta+1;
	  clk_480k_TMP <='0';
  end if;
end if;
end process;

process(clr, clk_480k_TMP)
variable ctb : std_logic_vector(1 downto 0);
begin
if clr='1' then
   ctb :="00";
elsif rising_edge(clk_480k_TMP) then
   if ctb ="10" then
	  ctb :="00";
   else
	   ctb := ctb +1;
   end if;
   clk_160k <= ctb(1);
end if;
end process;
clk_480k <= clk_480k_TMP;
dsp_clk_divout <= clk_16800k;
end Behavioral;