📄 dec3_8.rpt
字号:
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\yam\study\eda\eda\dec\dec3_8.rpt
dec3_8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 2/ 96( 2%) 4/ 48( 8%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\yam\study\eda\eda\dec\dec3_8.rpt
dec3_8
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
EN : INPUT;
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = _LC2_B20;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = _LC1_B20;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = _LC6_B20;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = _LC5_B20;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = _LC3_B10;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = _LC2_B10;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = _LC5_B10;
-- Node name is 'Y7'
-- Equation name is 'Y7', type is output
Y7 = _LC1_B10;
-- Node name is ':96'
-- Equation name is '_LC6_B10', type is buried
!_LC6_B10 = _LC6_B10~NOT;
_LC6_B10~NOT = LCELL( _EQ001);
_EQ001 = !A0
# !EN
# !A1
# !A2;
-- Node name is ':108'
-- Equation name is '_LC4_B20', type is buried
!_LC4_B20 = _LC4_B20~NOT;
_LC4_B20~NOT = LCELL( _EQ002);
_EQ002 = A0
# !EN
# !A1
# !A2;
-- Node name is ':120'
-- Equation name is '_LC8_B10', type is buried
!_LC8_B10 = _LC8_B10~NOT;
_LC8_B10~NOT = LCELL( _EQ003);
_EQ003 = !A0
# !EN
# A1
# !A2;
-- Node name is ':132'
-- Equation name is '_LC4_B10', type is buried
_LC4_B10 = LCELL( _EQ004);
_EQ004 = !A0 & !A1 & A2 & EN;
-- Node name is ':185'
-- Equation name is '_LC1_B10', type is buried
_LC1_B10 = LCELL( _EQ005);
_EQ005 = _LC3_B20 & !_LC4_B10 & !_LC4_B20 & !_LC8_B10;
-- Node name is ':212'
-- Equation name is '_LC5_B10', type is buried
_LC5_B10 = LCELL( _EQ006);
_EQ006 = _LC3_B20 & !_LC4_B10 & !_LC6_B10 & !_LC8_B10;
-- Node name is ':224'
-- Equation name is '_LC7_B10', type is buried
_LC7_B10 = LCELL( _EQ007);
_EQ007 = !_LC4_B20 & !_LC6_B10;
-- Node name is ':239'
-- Equation name is '_LC2_B10', type is buried
_LC2_B10 = LCELL( _EQ008);
_EQ008 = _LC3_B20 & !_LC4_B10 & _LC8_B10
# _LC3_B20 & !_LC4_B10 & _LC7_B10;
-- Node name is '~266~1'
-- Equation name is '~266~1', location is LC3_B20, type is buried.
-- synthesized logic cell
_LC3_B20 = LCELL( _EQ009);
_EQ009 = !EN
# A2;
-- Node name is ':266'
-- Equation name is '_LC3_B10', type is buried
_LC3_B10 = LCELL( _EQ010);
_EQ010 = _LC3_B20 & _LC4_B10
# _LC3_B20 & _LC7_B10 & !_LC8_B10;
-- Node name is ':293'
-- Equation name is '_LC5_B20', type is buried
_LC5_B20 = LCELL( _EQ011);
_EQ011 = !EN
# A0 & A1 & !A2;
-- Node name is ':320'
-- Equation name is '_LC6_B20', type is buried
_LC6_B20 = LCELL( _EQ012);
_EQ012 = !EN
# !A0 & A1 & !A2;
-- Node name is ':347'
-- Equation name is '_LC1_B20', type is buried
_LC1_B20 = LCELL( _EQ013);
_EQ013 = !EN
# A0 & !A1 & !A2;
-- Node name is ':372'
-- Equation name is '_LC2_B20', type is buried
_LC2_B20 = LCELL( _EQ014);
_EQ014 = !EN
# !A0 & !A1 & !A2;
Project Information f:\yam\study\eda\eda\dec\dec3_8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,802K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -